| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FastISel.cpp | [all...] |
| ScheduleDAGSDNodes.cpp | 125 if (ResNo >= II.getNumDefs() &&
126 II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) {
459 if (NumUsed > TII->get(N->getMachineOpcode()).getNumDefs())
550 unsigned NRegDefs = SchedDAG->TII->get(Node->getMachineOpcode()).getNumDefs();
637 OpIdx += TII->get(Use->getMachineOpcode()).getNumDefs();
[all...] |
| InstrEmitter.cpp | 134 if (i+II.getNumDefs() < II.getNumOperands()) {
136 TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF));
215 for (unsigned i = 0; i < II.getNumDefs(); ++i) {
738 unsigned NumDefs = II.getNumDefs();
[all...] |
| ScheduleDAGRRList.cpp | [all...] |
| ResourcePriorityQueue.cpp | 559 NodeNumDefs = std::min(N->getNumValues(), TID.getNumDefs());
|
| ScheduleDAGFast.cpp | 438 unsigned NumRes = MCID.getNumDefs();
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64DeadRegisterDefinitionsPass.cpp | 78 for (int i = 0, e = MI.getDesc().getNumDefs(); i != e; ++i) {
|
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstr.h | 323 operands_begin(), operands_begin() + getDesc().getNumDefs());
327 operands_begin(), operands_begin() + getDesc().getNumDefs());
331 operands_begin() + getDesc().getNumDefs(), operands_end());
335 operands_begin() + getDesc().getNumDefs(), operands_end());
[all...] |
| /external/llvm/lib/CodeGen/ |
| ExecutionDepsFix.cpp | 507 e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs();
580 for (unsigned i = mi->getDesc().getNumDefs(),
590 for (unsigned i = 0, e = mi->getDesc().getNumDefs(); i != e; ++i) {
609 for (unsigned i = mi->getDesc().getNumDefs(),
|
| PeepholeOptimizer.cpp | 500 if (Copy.getDesc().getNumDefs() != 1)
607 if (MCID.getNumDefs() != 1)
629 if (MCID.getNumDefs() != 1)
742 for (unsigned i = MIDesc.getNumDefs(); i != MIDesc.getNumOperands();
810 if (Def->getDesc().getNumDefs() != 1)
[all...] |
| TargetInstrInfo.cpp | 124 bool HasDef = MCID.getNumDefs();
191 SrcOpIdx1 = MCID.getNumDefs();
|
| MachineCSE.cpp | 522 unsigned NumDefs = MI->getDesc().getNumDefs() +
|
| MachineLICM.cpp | [all...] |
| MachineVerifier.cpp | 821 if (MONum < MCID.getNumDefs()) {
875 if (MONum < MCID.getNumDefs()) {
[all...] |
| RegAllocFast.cpp | [all...] |
| RegisterCoalescer.cpp | 762 if (MCID.getNumDefs() != 1)
[all...] |
| TwoAddressInstructionPass.cpp | [all...] |
| /external/llvm/include/llvm/MC/ |
| MCInstrDesc.h | 198 unsigned getNumDefs() const {
|
| /external/llvm/lib/Target/ARM/ |
| ARMFastISel.cpp | 295 if (II.getNumDefs() >= 1) {
320 if (II.getNumDefs() >= 1) {
350 if (II.getNumDefs() >= 1) {
378 if (II.getNumDefs() >= 1) {
406 if (II.getNumDefs() >= 1) {
430 if (II.getNumDefs() >= 1) {
[all...] |
| ARMCodeEmitter.cpp | [all...] |
| ARMBaseInstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.cpp | [all...] |
| AMDGPUISelDAGToDAG.cpp | 129 unsigned OpIdx = Desc.getNumDefs() + OpNo;
|
| /external/llvm/lib/MC/MCParser/ |
| AsmParser.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | [all...] |
