| /external/llvm/lib/Target/Sparc/ |
| SparcInstrVIS.td | 15 class VISInstFormat<bits<9> opfval, dag outs, dag ins, string asmstr,
17 : F3_3<0b10, 0b110110, opfval, outs, ins, asmstr, pattern>;
21 (outs RC:$rd), (ins RC:$rs1, RC:$rs2),
27 (outs I64Regs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
33 : VISInstFormat<opfval, (outs), (ins), asmstr, []>;
39 (outs RC:$rd), (ins RC:$rs1),
46 (outs RC:$rd), (ins RC:$rs2),
53 (outs RC:$rd), (ins RC:$f),
175 def CMASK8 : VISInstFormat<0b000011011, (outs), (ins I64Regs:$rs2),
177 def CMASK16 : VISInstFormat<0b000011101, (outs), (ins I64Regs:$rs2)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrXOP.td | 15 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
18 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
42 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
45 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins memop:$src),
57 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
60 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
70 def rrY : IXOP<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
73 def rmY : IXOP<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
82 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst),
86 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst)
[all...] |
| X86InstrMMX.td | 93 def irr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
100 def irm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
111 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
116 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
122 def ri : MMXIi8<opc2, ImmForm, (outs VR64:$dst),
133 def rr64 : MMXSS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
138 def rm64 : MMXSS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
150 def rr64 : MMXSS38I<opc, MRMSrcReg, (outs VR64:$dst),
155 def rm64 : MMXSS38I<opc, MRMSrcMem, (outs VR64:$dst),
167 def R64irr : MMXSS3AI<0x0F, MRMSrcReg, (outs VR64:$dst)
[all...] |
| X86InstrInfo.td | [all...] |
| X86InstrArithmetic.td | 20 (outs GR16:$dst), (ins i32mem:$src),
24 (outs GR32:$dst), (ins i32mem:$src),
30 (outs GR32:$dst), (ins lea64_32mem:$src),
36 def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins lea64mem:$src),
61 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
69 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
74 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
80 def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src),
86 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
96 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrAltivec.td | 182 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC),
190 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC),
198 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC),
205 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
213 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
221 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
227 : VXForm_2<xo, (outs vrrc:$vD), (ins vrrc:$vB),
235 : VXForm_2<xo, (outs vrrc:$vD), (ins vrrc:$vB),
246 def DSS : DSS_Form<822, (outs),
250 def DSSALL : DSS_Form<822, (outs),
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonIntrinsicsV4.td | 21 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
26 : ALU32_rr<(outs DoubleRegs:$dst), (ins s8Imm:$src1, IntRegs:$src2),
31 : ALU32_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2),
36 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
41 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, s10Imm:$src2),
46 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, u9Imm:$src2),
51 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
56 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2),
61 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2),
70 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2)
[all...] |
| /external/llvm/tools/bugpoint/ |
| BugDriver.cpp | 126 outs() << "Read input file : '" << Filenames[0] << "'\n";
132 outs() << "Linking in input file: '" << Filenames[i] << "'\n";
142 outs() << "*** All input ok\n";
168 outs() << "Running selected passes on program to test for crash: ";
177 outs() << "Running the code generator to test for a crash: ";
181 outs() << Error;
184 outs() << '\n';
192 outs() << "Generating reference output from raw program: ";
207 outs() << "*** Checking the code generator...\n";
214 outs() << "\n*** Output matches: Debugging miscompilation!\n"
[all...] |
| /frameworks/rs/cpu_ref/ |
| rsCpuScriptGroup.cpp | 86 if (sl->outs[ct]) {
87 mp->ptrOut = (uint8_t *)sl->outs[ct]->mHal.drvState.lod[0].mallocPtr;
89 ostep = sl->outs[ct]->mHal.state.elementSizeBytes;
91 mp->out = mp->ptrOut + sl->outs[ct]->mHal.drvState.lod[0].stride * p->y;
93 if (sl->outs[ct]->mHal.drvState.lod[0].dimY > p->lid) {
94 mp->out = mp->ptrOut + sl->outs[ct]->mHal.drvState.lod[0].stride * p->lid;
114 Vector<Allocation *> outs; local
184 outs.add(aout);
199 si->forEachMtlsSetup(ins[ct], outs[ct], NULL, 0, NULL, &mtls);
201 si->preLaunch(slot, ins[ct], outs[ct], mtls.fep.usr, mtls.fep.usrLen, NULL)
[all...] |
| /dalvik/dx/tests/062-dex-synch-method/ |
| expected.txt | 2 regs: 0003; ins: 0001; outs: 0000
9 regs: 0006; ins: 0002; outs: 0001
27 regs: 000b; ins: 0004; outs: 0000
45 regs: 000b; ins: 0003; outs: 0000
62 regs: 0004; ins: 0001; outs: 0001
78 regs: 0002; ins: 0000; outs: 0000
84 regs: 0004; ins: 0001; outs: 0001
101 regs: 0009; ins: 0003; outs: 0000
118 regs: 0009; ins: 0002; outs: 0000
134 regs: 0002; ins: 0000; outs: 000
[all...] |
| /external/clang/lib/StaticAnalyzer/Checkers/ |
| TraversalChecker.cpp | 45 // It is mildly evil to print directly to llvm::outs() rather than emitting
49 llvm::outs() << C.getSourceManager().getSpellingLineNumber(Loc) << " "
54 llvm::outs() << "--END FUNCTION--\n";
78 // It is mildly evil to print directly to llvm::outs() rather than emitting
81 llvm::outs().indent(Indentation);
82 Call.dump(llvm::outs());
95 // It is mildly evil to print directly to llvm::outs() rather than emitting
98 llvm::outs().indent(Indentation);
100 llvm::outs() << "Returning void\n";
102 llvm::outs() << "Returning " << C.getSVal(CallE) << "\n"
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| SIInstrInfo.td | 31 class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
32 AMDGPUInst<outs, ins, asm, pattern> {
42 class Enc32 <dag outs, dag ins, string asm, list<dag> pattern> :
43 InstSI <outs, ins, asm, pattern> {
48 class Enc64 <dag outs, dag ins, string asm, list<dag> pattern> :
49 InstSI <outs, ins, asm, pattern> {
113 (outs),
145 class MIMG <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
146 Enc64 <outs, ins, asm, pattern> {
182 class MTBUF <bits<3> op, dag outs, dag ins, string asm, list<dag> pattern>
[all...] |
| /external/llvm/lib/Target/R600/ |
| SIInstrFormats.td | 14 class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
15 AMDGPUInst<outs, ins, asm, pattern>, PredicateControl {
40 class Enc32 <dag outs, dag ins, string asm, list<dag> pattern> :
41 InstSI <outs, ins, asm, pattern> {
47 class Enc64 <dag outs, dag ins, string asm, list<dag> pattern> :
48 InstSI <outs, ins, asm, pattern> {
54 class VOP3Common <dag outs, dag ins, string asm, list<dag> pattern> :
55 Enc64 <outs, ins, asm, pattern> {
68 class SOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
69 Enc32<outs, ins, asm, pattern>
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIInstrInfo.td | 31 class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
32 AMDGPUInst<outs, ins, asm, pattern> {
42 class Enc32 <dag outs, dag ins, string asm, list<dag> pattern> :
43 InstSI <outs, ins, asm, pattern> {
48 class Enc64 <dag outs, dag ins, string asm, list<dag> pattern> :
49 InstSI <outs, ins, asm, pattern> {
113 (outs),
145 class MIMG <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
146 Enc64 <outs, ins, asm, pattern> {
182 class MTBUF <bits<3> op, dag outs, dag ins, string asm, list<dag> pattern>
[all...] |
| /dalvik/dx/tests/078-dex-local-variable-table/ |
| expected.txt | 2 regs: 0003; ins: 0001; outs: 0001
17 regs: 0003; ins: 0000; outs: 0000
35 regs: 0004; ins: 0001; outs: 0000
55 regs: 0004; ins: 0001; outs: 0000
79 regs: 0006; ins: 0001; outs: 0000
107 regs: 0005; ins: 0001; outs: 0000
140 regs: 0004; ins: 0001; outs: 0000
156 regs: 0004; ins: 0001; outs: 0000
172 regs: 0004; ins: 0001; outs: 0000
188 regs: 0008; ins: 0002; outs: 000
[all...] |
| /external/llvm/tools/llvm-nm/ |
| llvm-nm.cpp | 294 outs() << SymbolAddrStr << ' ';
300 outs() << "(common) ";
302 outs() << "(alignment 2^" << (int)MachO::GET_COMM_ALIGN(NDesc) << ") ";
305 outs() << "(prebound ";
307 outs() << "(";
310 outs() << "undefined [lazy bound]) ";
313 outs() << "undefined [private lazy bound]) ";
316 outs() << "undefined [private]) ";
318 outs() << "undefined) ";
322 outs() << "(absolute) "
[all...] |
| /external/llvm/lib/CodeGen/ |
| CallingConvLower.cpp | 86 bool CCState::CheckReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
89 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
90 MVT VT = Outs[i].VT;
91 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
100 void CCState::AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
103 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
104 MVT VT = Outs[i].VT;
105 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
118 void CCState::AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
120 unsigned NumOps = Outs.size()
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMInstrThumb.td | 256 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
261 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
272 def tHINT : T1pI<(outs), (ins imm0_15:$imm), NoItinerary, "hint", "\t$imm",
295 def tBKPT : T1I<(outs), (ins imm0_255:$val), NoItinerary, "bkpt\t$val",
306 def tHLT : T1I<(outs), (ins imm0_63:$val), NoItinerary, "hlt\t$val",
313 def tSETEND : T1I<(outs), (ins setend_op:$end), NoItinerary, "setend\t$end",
324 def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags),
339 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
352 def tADDrSPi : T1pI<(outs tGPR:$dst), (ins GPRsp:$sp, t_imm0_1020s4:$imm),
364 def tADDspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm)
[all...] |
| /dalvik/dx/tests/057-dex-call-virtual/ |
| expected.txt | 2 regs: 0004; ins: 0001; outs: 0002
|
| /dalvik/dx/tests/058-dex-call-direct/ |
| expected.txt | 2 regs: 0004; ins: 0001; outs: 0002
|
| /dalvik/dx/tests/071-dex-java-stack-ops/ |
| expected.txt | 2 regs: 0003; ins: 0000; outs: 0001
11 regs: 0006; ins: 0000; outs: 0001
26 regs: 0006; ins: 0000; outs: 0002
35 regs: 0008; ins: 0000; outs: 0001
54 regs: 0008; ins: 0000; outs: 0002
67 regs: 000a; ins: 0000; outs: 0001
90 regs: 000a; ins: 0000; outs: 0002
107 regs: 000a; ins: 0000; outs: 0002
126 regs: 000a; ins: 0000; outs: 0002
139 regs: 0005; ins: 0000; outs: 000
[all...] |
| /dalvik/dx/tests/075-dex-cat2-value-merge/ |
| expected.txt | 2 regs: 0008; ins: 0001; outs: 0000
|
| /external/llvm/test/TableGen/ |
| cast.td | 31 def outs;
73 def PS : Inst<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
77 def PD : Inst<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
85 Inst<opcode,(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
| /external/llvm/tools/llvm-objdump/ |
| llvm-objdump.cpp | 155 outs() << ToolName << ": error reading file: " << EC.message() << ".\n";
156 outs().flush();
264 outs() << output;
361 outs() << "Atom " << (*AI)->getName() << ": \n";
366 IP->printInst(&II->Inst, outs(), "");
367 outs() << "\n";
466 outs() << "Disassembly of section ";
468 outs() << SegmentName << ",";
469 outs() << name << ':';
504 outs() << '\n' << Symbols[si].second << ":\n"
[all...] |
| /dalvik/dx/tests/064-dex-array-access/ |
| expected.txt | 2 regs: 0007; ins: 0002; outs: 0000
15 regs: 0007; ins: 0002; outs: 0000
28 regs: 0007; ins: 0002; outs: 0000
41 regs: 0007; ins: 0002; outs: 0000
54 regs: 0007; ins: 0002; outs: 0000
67 regs: 0008; ins: 0002; outs: 0000
80 regs: 0007; ins: 0002; outs: 0000
93 regs: 0008; ins: 0002; outs: 0000
106 regs: 0007; ins: 0002; outs: 0000
119 regs: 0005; ins: 0001; outs: 000
[all...] |
