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      1 //===-- SparcISelDAGToDAG.cpp - A dag to dag inst selector for Sparc ------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file defines an instruction selector for the SPARC target.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #include "SparcTargetMachine.h"
     15 #include "llvm/CodeGen/SelectionDAGISel.h"
     16 #include "llvm/IR/Intrinsics.h"
     17 #include "llvm/Support/Compiler.h"
     18 #include "llvm/Support/Debug.h"
     19 #include "llvm/Support/ErrorHandling.h"
     20 #include "llvm/Support/raw_ostream.h"
     21 using namespace llvm;
     22 
     23 //===----------------------------------------------------------------------===//
     24 // Instruction Selector Implementation
     25 //===----------------------------------------------------------------------===//
     26 
     27 //===--------------------------------------------------------------------===//
     28 /// SparcDAGToDAGISel - SPARC specific code to select SPARC machine
     29 /// instructions for SelectionDAG operations.
     30 ///
     31 namespace {
     32 class SparcDAGToDAGISel : public SelectionDAGISel {
     33   /// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can
     34   /// make the right decision when generating code for different targets.
     35   const SparcSubtarget &Subtarget;
     36   SparcTargetMachine &TM;
     37 public:
     38   explicit SparcDAGToDAGISel(SparcTargetMachine &tm)
     39     : SelectionDAGISel(tm),
     40       Subtarget(tm.getSubtarget<SparcSubtarget>()),
     41       TM(tm) {
     42   }
     43 
     44   SDNode *Select(SDNode *N) override;
     45 
     46   // Complex Pattern Selectors.
     47   bool SelectADDRrr(SDValue N, SDValue &R1, SDValue &R2);
     48   bool SelectADDRri(SDValue N, SDValue &Base, SDValue &Offset);
     49 
     50   /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
     51   /// inline asm expressions.
     52   bool SelectInlineAsmMemoryOperand(const SDValue &Op,
     53                                     char ConstraintCode,
     54                                     std::vector<SDValue> &OutOps) override;
     55 
     56   const char *getPassName() const override {
     57     return "SPARC DAG->DAG Pattern Instruction Selection";
     58   }
     59 
     60   // Include the pieces autogenerated from the target description.
     61 #include "SparcGenDAGISel.inc"
     62 
     63 private:
     64   SDNode* getGlobalBaseReg();
     65 };
     66 }  // end anonymous namespace
     67 
     68 SDNode* SparcDAGToDAGISel::getGlobalBaseReg() {
     69   unsigned GlobalBaseReg = TM.getInstrInfo()->getGlobalBaseReg(MF);
     70   return CurDAG->getRegister(GlobalBaseReg,
     71                              getTargetLowering()->getPointerTy()).getNode();
     72 }
     73 
     74 bool SparcDAGToDAGISel::SelectADDRri(SDValue Addr,
     75                                      SDValue &Base, SDValue &Offset) {
     76   if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
     77     Base = CurDAG->getTargetFrameIndex(FIN->getIndex(),
     78                                        getTargetLowering()->getPointerTy());
     79     Offset = CurDAG->getTargetConstant(0, MVT::i32);
     80     return true;
     81   }
     82   if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
     83       Addr.getOpcode() == ISD::TargetGlobalAddress ||
     84       Addr.getOpcode() == ISD::TargetGlobalTLSAddress)
     85     return false;  // direct calls.
     86 
     87   if (Addr.getOpcode() == ISD::ADD) {
     88     if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
     89       if (isInt<13>(CN->getSExtValue())) {
     90         if (FrameIndexSDNode *FIN =
     91                 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
     92           // Constant offset from frame ref.
     93           Base = CurDAG->getTargetFrameIndex(FIN->getIndex(),
     94                                            getTargetLowering()->getPointerTy());
     95         } else {
     96           Base = Addr.getOperand(0);
     97         }
     98         Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
     99         return true;
    100       }
    101     }
    102     if (Addr.getOperand(0).getOpcode() == SPISD::Lo) {
    103       Base = Addr.getOperand(1);
    104       Offset = Addr.getOperand(0).getOperand(0);
    105       return true;
    106     }
    107     if (Addr.getOperand(1).getOpcode() == SPISD::Lo) {
    108       Base = Addr.getOperand(0);
    109       Offset = Addr.getOperand(1).getOperand(0);
    110       return true;
    111     }
    112   }
    113   Base = Addr;
    114   Offset = CurDAG->getTargetConstant(0, MVT::i32);
    115   return true;
    116 }
    117 
    118 bool SparcDAGToDAGISel::SelectADDRrr(SDValue Addr, SDValue &R1, SDValue &R2) {
    119   if (Addr.getOpcode() == ISD::FrameIndex) return false;
    120   if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
    121       Addr.getOpcode() == ISD::TargetGlobalAddress ||
    122       Addr.getOpcode() == ISD::TargetGlobalTLSAddress)
    123     return false;  // direct calls.
    124 
    125   if (Addr.getOpcode() == ISD::ADD) {
    126     if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
    127       if (isInt<13>(CN->getSExtValue()))
    128         return false;  // Let the reg+imm pattern catch this!
    129     if (Addr.getOperand(0).getOpcode() == SPISD::Lo ||
    130         Addr.getOperand(1).getOpcode() == SPISD::Lo)
    131       return false;  // Let the reg+imm pattern catch this!
    132     R1 = Addr.getOperand(0);
    133     R2 = Addr.getOperand(1);
    134     return true;
    135   }
    136 
    137   R1 = Addr;
    138   R2 = CurDAG->getRegister(SP::G0, getTargetLowering()->getPointerTy());
    139   return true;
    140 }
    141 
    142 SDNode *SparcDAGToDAGISel::Select(SDNode *N) {
    143   SDLoc dl(N);
    144   if (N->isMachineOpcode()) {
    145     N->setNodeId(-1);
    146     return nullptr;   // Already selected.
    147   }
    148 
    149   switch (N->getOpcode()) {
    150   default: break;
    151   case SPISD::GLOBAL_BASE_REG:
    152     return getGlobalBaseReg();
    153 
    154   case ISD::SDIV:
    155   case ISD::UDIV: {
    156     // sdivx / udivx handle 64-bit divides.
    157     if (N->getValueType(0) == MVT::i64)
    158       break;
    159     // FIXME: should use a custom expander to expose the SRA to the dag.
    160     SDValue DivLHS = N->getOperand(0);
    161     SDValue DivRHS = N->getOperand(1);
    162 
    163     // Set the Y register to the high-part.
    164     SDValue TopPart;
    165     if (N->getOpcode() == ISD::SDIV) {
    166       TopPart = SDValue(CurDAG->getMachineNode(SP::SRAri, dl, MVT::i32, DivLHS,
    167                                    CurDAG->getTargetConstant(31, MVT::i32)), 0);
    168     } else {
    169       TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
    170     }
    171     TopPart = SDValue(CurDAG->getMachineNode(SP::WRYrr, dl, MVT::Glue, TopPart,
    172                                      CurDAG->getRegister(SP::G0, MVT::i32)), 0);
    173 
    174     // FIXME: Handle div by immediate.
    175     unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
    176     return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS,
    177                                 TopPart);
    178   }
    179   case ISD::MULHU:
    180   case ISD::MULHS: {
    181     // FIXME: Handle mul by immediate.
    182     SDValue MulLHS = N->getOperand(0);
    183     SDValue MulRHS = N->getOperand(1);
    184     unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
    185     SDNode *Mul = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::Glue,
    186                                          MulLHS, MulRHS);
    187     // The high part is in the Y register.
    188     return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDValue(Mul, 1));
    189   }
    190   }
    191 
    192   return SelectCode(N);
    193 }
    194 
    195 
    196 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
    197 /// inline asm expressions.
    198 bool
    199 SparcDAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op,
    200                                                 char ConstraintCode,
    201                                                 std::vector<SDValue> &OutOps) {
    202   SDValue Op0, Op1;
    203   switch (ConstraintCode) {
    204   default: return true;
    205   case 'm':   // memory
    206    if (!SelectADDRrr(Op, Op0, Op1))
    207      SelectADDRri(Op, Op0, Op1);
    208    break;
    209   }
    210 
    211   OutOps.push_back(Op0);
    212   OutOps.push_back(Op1);
    213   return false;
    214 }
    215 
    216 /// createSparcISelDag - This pass converts a legalized DAG into a
    217 /// SPARC-specific DAG, ready for instruction scheduling.
    218 ///
    219 FunctionPass *llvm::createSparcISelDag(SparcTargetMachine &TM) {
    220   return new SparcDAGToDAGISel(TM);
    221 }
    222