1 //===-- X86RegisterInfo.h - X86 Register Information Impl -------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the X86 implementation of the TargetRegisterInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef X86REGISTERINFO_H 15 #define X86REGISTERINFO_H 16 17 #include "llvm/Target/TargetRegisterInfo.h" 18 19 #define GET_REGINFO_HEADER 20 #include "X86GenRegisterInfo.inc" 21 22 namespace llvm { 23 class Type; 24 class TargetInstrInfo; 25 class X86Subtarget; 26 27 class X86RegisterInfo final : public X86GenRegisterInfo { 28 public: 29 const X86Subtarget &Subtarget; 30 31 private: 32 /// Is64Bit - Is the target 64-bits. 33 /// 34 bool Is64Bit; 35 36 /// IsWin64 - Is the target on of win64 flavours 37 /// 38 bool IsWin64; 39 40 /// SlotSize - Stack slot size in bytes. 41 /// 42 unsigned SlotSize; 43 44 /// StackPtr - X86 physical register used as stack ptr. 45 /// 46 unsigned StackPtr; 47 48 /// FramePtr - X86 physical register used as frame ptr. 49 /// 50 unsigned FramePtr; 51 52 /// BasePtr - X86 physical register used as a base ptr in complex stack 53 /// frames. I.e., when we need a 3rd base, not just SP and FP, due to 54 /// variable size stack objects. 55 unsigned BasePtr; 56 57 public: 58 X86RegisterInfo(const X86Subtarget &STI); 59 60 // FIXME: This should be tablegen'd like getDwarfRegNum is 61 int getSEHRegNum(unsigned i) const; 62 63 /// Code Generation virtual methods... 64 /// 65 bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override; 66 67 /// getMatchingSuperRegClass - Return a subclass of the specified register 68 /// class A so that each register in it has a sub-register of the 69 /// specified sub-register index which is in the specified register class B. 70 const TargetRegisterClass * 71 getMatchingSuperRegClass(const TargetRegisterClass *A, 72 const TargetRegisterClass *B, 73 unsigned Idx) const override; 74 75 const TargetRegisterClass * 76 getSubClassWithSubReg(const TargetRegisterClass *RC, 77 unsigned Idx) const override; 78 79 const TargetRegisterClass* 80 getLargestLegalSuperClass(const TargetRegisterClass *RC) const override; 81 82 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 83 /// values. 84 const TargetRegisterClass * 85 getPointerRegClass(const MachineFunction &MF, 86 unsigned Kind = 0) const override; 87 88 /// getCrossCopyRegClass - Returns a legal register class to copy a register 89 /// in the specified class to or from. Returns NULL if it is possible to copy 90 /// between a two registers of the specified class. 91 const TargetRegisterClass * 92 getCrossCopyRegClass(const TargetRegisterClass *RC) const override; 93 94 unsigned getRegPressureLimit(const TargetRegisterClass *RC, 95 MachineFunction &MF) const override; 96 97 /// getCalleeSavedRegs - Return a null-terminated list of all of the 98 /// callee-save registers on this target. 99 const MCPhysReg * 100 getCalleeSavedRegs(const MachineFunction* MF) const override; 101 const uint32_t *getCallPreservedMask(CallingConv::ID) const override; 102 const uint32_t *getNoPreservedMask() const; 103 104 /// getReservedRegs - Returns a bitset indexed by physical register number 105 /// indicating if a register is a special register that has particular uses and 106 /// should be considered unavailable at all times, e.g. SP, RA. This is used by 107 /// register scavenger to determine what registers are free. 108 BitVector getReservedRegs(const MachineFunction &MF) const override; 109 110 bool hasBasePointer(const MachineFunction &MF) const; 111 112 bool canRealignStack(const MachineFunction &MF) const; 113 114 bool needsStackRealignment(const MachineFunction &MF) const override; 115 116 bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, 117 int &FrameIdx) const override; 118 119 void eliminateFrameIndex(MachineBasicBlock::iterator MI, 120 int SPAdj, unsigned FIOperandNum, 121 RegScavenger *RS = nullptr) const override; 122 123 // Debug information queries. 124 unsigned getFrameRegister(const MachineFunction &MF) const override; 125 unsigned getStackRegister() const { return StackPtr; } 126 unsigned getBaseRegister() const { return BasePtr; } 127 // FIXME: Move to FrameInfok 128 unsigned getSlotSize() const { return SlotSize; } 129 }; 130 131 // getX86SubSuperRegister - X86 utility function. It returns the sub or super 132 // register of a specific X86 register. 133 // e.g. getX86SubSuperRegister(X86::EAX, MVT::i16) return X86:AX 134 unsigned getX86SubSuperRegister(unsigned, MVT::SimpleValueType, bool High=false); 135 136 //get512BitRegister - X86 utility - returns 512-bit super register 137 unsigned get512BitSuperRegister(unsigned Reg); 138 139 } // End llvm namespace 140 141 #endif 142
