1 //===-- XCoreInstrInfo.h - XCore Instruction Information --------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the XCore implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef XCOREINSTRUCTIONINFO_H 15 #define XCOREINSTRUCTIONINFO_H 16 17 #include "XCoreRegisterInfo.h" 18 #include "llvm/Target/TargetInstrInfo.h" 19 20 #define GET_INSTRINFO_HEADER 21 #include "XCoreGenInstrInfo.inc" 22 23 namespace llvm { 24 25 class XCoreInstrInfo : public XCoreGenInstrInfo { 26 const XCoreRegisterInfo RI; 27 virtual void anchor(); 28 public: 29 XCoreInstrInfo(); 30 31 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 32 /// such, whenever a client has an instance of instruction info, it should 33 /// always be able to get register info as well (through this method). 34 /// 35 const TargetRegisterInfo &getRegisterInfo() const { return RI; } 36 37 /// isLoadFromStackSlot - If the specified machine instruction is a direct 38 /// load from a stack slot, return the virtual or physical register number of 39 /// the destination along with the FrameIndex of the loaded stack slot. If 40 /// not, return 0. This predicate must return 0 if the instruction has 41 /// any side effects other than loading from the stack slot. 42 unsigned isLoadFromStackSlot(const MachineInstr *MI, 43 int &FrameIndex) const override; 44 45 /// isStoreToStackSlot - If the specified machine instruction is a direct 46 /// store to a stack slot, return the virtual or physical register number of 47 /// the source reg along with the FrameIndex of the loaded stack slot. If 48 /// not, return 0. This predicate must return 0 if the instruction has 49 /// any side effects other than storing to the stack slot. 50 unsigned isStoreToStackSlot(const MachineInstr *MI, 51 int &FrameIndex) const override; 52 53 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 54 MachineBasicBlock *&FBB, 55 SmallVectorImpl<MachineOperand> &Cond, 56 bool AllowModify) const override; 57 58 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 59 MachineBasicBlock *FBB, 60 const SmallVectorImpl<MachineOperand> &Cond, 61 DebugLoc DL) const override; 62 63 unsigned RemoveBranch(MachineBasicBlock &MBB) const override; 64 65 void copyPhysReg(MachineBasicBlock &MBB, 66 MachineBasicBlock::iterator I, DebugLoc DL, 67 unsigned DestReg, unsigned SrcReg, 68 bool KillSrc) const override; 69 70 void storeRegToStackSlot(MachineBasicBlock &MBB, 71 MachineBasicBlock::iterator MI, 72 unsigned SrcReg, bool isKill, int FrameIndex, 73 const TargetRegisterClass *RC, 74 const TargetRegisterInfo *TRI) const override; 75 76 void loadRegFromStackSlot(MachineBasicBlock &MBB, 77 MachineBasicBlock::iterator MI, 78 unsigned DestReg, int FrameIndex, 79 const TargetRegisterClass *RC, 80 const TargetRegisterInfo *TRI) const override; 81 82 bool ReverseBranchCondition( 83 SmallVectorImpl<MachineOperand> &Cond) const override; 84 85 // Emit code before MBBI to load immediate value into physical register Reg. 86 // Returns an iterator to the new instruction. 87 MachineBasicBlock::iterator loadImmediate(MachineBasicBlock &MBB, 88 MachineBasicBlock::iterator MI, 89 unsigned Reg, uint64_t Value) const; 90 }; 91 92 } 93 94 #endif 95
