1 /* 2 Copyright (C) Intel Corp. 2006. All Rights Reserved. 3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to 4 develop this 3D driver. 5 6 Permission is hereby granted, free of charge, to any person obtaining 7 a copy of this software and associated documentation files (the 8 "Software"), to deal in the Software without restriction, including 9 without limitation the rights to use, copy, modify, merge, publish, 10 distribute, sublicense, and/or sell copies of the Software, and to 11 permit persons to whom the Software is furnished to do so, subject to 12 the following conditions: 13 14 The above copyright notice and this permission notice (including the 15 next paragraph) shall be included in all copies or substantial 16 portions of the Software. 17 18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 26 **********************************************************************/ 27 /* 28 * Authors: 29 * Keith Whitwell <keith (at) tungstengraphics.com> 30 */ 31 32 /* Code to layout images in a mipmap tree for i965. 33 */ 34 35 #include "intel_mipmap_tree.h" 36 #include "intel_tex_layout.h" 37 #include "intel_context.h" 38 #include "main/macros.h" 39 40 #define FILE_DEBUG_FLAG DEBUG_MIPTREE 41 42 static void 43 brw_miptree_layout_texture_array(struct intel_context *intel, 44 struct intel_mipmap_tree *mt) 45 { 46 GLuint level; 47 GLuint qpitch = 0; 48 int h0, h1, q; 49 50 h0 = ALIGN(mt->height0, mt->align_h); 51 h1 = ALIGN(minify(mt->height0), mt->align_h); 52 if (mt->array_spacing_lod0) 53 qpitch = h0; 54 else 55 qpitch = (h0 + h1 + (intel->gen >= 7 ? 12 : 11) * mt->align_h); 56 if (mt->compressed) 57 qpitch /= 4; 58 59 i945_miptree_layout_2d(mt); 60 61 for (level = mt->first_level; level <= mt->last_level; level++) { 62 for (q = 0; q < mt->depth0; q++) { 63 intel_miptree_set_image_offset(mt, level, q, 0, q * qpitch); 64 } 65 } 66 mt->total_height = qpitch * mt->depth0; 67 } 68 69 void 70 brw_miptree_layout(struct intel_context *intel, struct intel_mipmap_tree *mt) 71 { 72 switch (mt->target) { 73 case GL_TEXTURE_CUBE_MAP: 74 if (intel->gen >= 5) { 75 /* On Ironlake, cube maps are finally represented as just a series of 76 * MIPLAYOUT_BELOW 2D textures (like 2D texture arrays), separated by a 77 * pitch of qpitch rows, where qpitch is defined by the equation given 78 * in Volume 1 of the BSpec. 79 */ 80 brw_miptree_layout_texture_array(intel, mt); 81 break; 82 } 83 assert(mt->depth0 == 6); 84 /* FALLTHROUGH */ 85 86 case GL_TEXTURE_3D: { 87 GLuint width = mt->width0; 88 GLuint height = mt->height0; 89 GLuint depth = mt->depth0; 90 GLuint pack_x_pitch, pack_x_nr; 91 GLuint pack_y_pitch; 92 GLuint level; 93 94 mt->total_height = 0; 95 96 if (mt->compressed) { 97 mt->total_width = ALIGN(width, mt->align_w); 98 pack_y_pitch = (height + 3) / 4; 99 } else { 100 mt->total_width = mt->width0; 101 pack_y_pitch = ALIGN(mt->height0, mt->align_h); 102 } 103 104 pack_x_pitch = width; 105 pack_x_nr = 1; 106 107 for (level = mt->first_level ; level <= mt->last_level ; level++) { 108 GLint x = 0; 109 GLint y = 0; 110 GLint q, j; 111 112 intel_miptree_set_level_info(mt, level, 113 0, mt->total_height, 114 width, height, depth); 115 116 for (q = 0; q < depth; /* empty */) { 117 for (j = 0; j < pack_x_nr && q < depth; j++, q++) { 118 intel_miptree_set_image_offset(mt, level, q, x, y); 119 x += pack_x_pitch; 120 } 121 if (x > mt->total_width) 122 mt->total_width = x; 123 124 x = 0; 125 y += pack_y_pitch; 126 } 127 128 129 mt->total_height += y; 130 width = minify(width); 131 height = minify(height); 132 if (mt->target == GL_TEXTURE_3D) 133 depth = minify(depth); 134 135 if (mt->compressed) { 136 pack_y_pitch = (height + 3) / 4; 137 138 if (pack_x_pitch > ALIGN(width, mt->align_w)) { 139 pack_x_pitch = ALIGN(width, mt->align_w); 140 pack_x_nr <<= 1; 141 } 142 } else { 143 pack_x_nr <<= 1; 144 if (pack_x_pitch > 4) { 145 pack_x_pitch >>= 1; 146 } 147 148 if (pack_y_pitch > 2) { 149 pack_y_pitch >>= 1; 150 pack_y_pitch = ALIGN(pack_y_pitch, mt->align_h); 151 } 152 } 153 154 } 155 /* The 965's sampler lays cachelines out according to how accesses 156 * in the texture surfaces run, so they may be "vertical" through 157 * memory. As a result, the docs say in Surface Padding Requirements: 158 * Sampling Engine Surfaces that two extra rows of padding are required. 159 */ 160 if (mt->target == GL_TEXTURE_CUBE_MAP) 161 mt->total_height += 2; 162 break; 163 } 164 165 case GL_TEXTURE_2D_ARRAY: 166 case GL_TEXTURE_1D_ARRAY: 167 brw_miptree_layout_texture_array(intel, mt); 168 break; 169 170 default: 171 switch (mt->msaa_layout) { 172 case INTEL_MSAA_LAYOUT_UMS: 173 case INTEL_MSAA_LAYOUT_CMS: 174 brw_miptree_layout_texture_array(intel, mt); 175 break; 176 case INTEL_MSAA_LAYOUT_NONE: 177 case INTEL_MSAA_LAYOUT_IMS: 178 i945_miptree_layout_2d(mt); 179 break; 180 } 181 break; 182 } 183 DBG("%s: %dx%dx%d\n", __FUNCTION__, 184 mt->total_width, mt->total_height, mt->cpp); 185 } 186 187
