1 /************************************************************************** 2 * 3 * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas. 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 /* 28 * Authors: 29 * Keith Whitwell <keith (at) tungstengraphics.com> 30 * Michel Dnzer <michel (at) tungstengraphics.com> 31 */ 32 33 #include "intel_mipmap_tree.h" 34 #include "intel_tex_layout.h" 35 #include "intel_context.h" 36 37 #include "main/image.h" 38 #include "main/macros.h" 39 40 static unsigned int 41 intel_horizontal_texture_alignment_unit(struct intel_context *intel, 42 gl_format format) 43 { 44 /** 45 * From the "Alignment Unit Size" section of various specs, namely: 46 * - Gen3 Spec: "Memory Data Formats" Volume, Section 1.20.1.4 47 * - i965 and G45 PRMs: Volume 1, Section 6.17.3.4. 48 * - Ironlake and Sandybridge PRMs: Volume 1, Part 1, Section 7.18.3.4 49 * - BSpec (for Ivybridge and slight variations in separate stencil) 50 * 51 * +----------------------------------------------------------------------+ 52 * | | alignment unit width ("i") | 53 * | Surface Property |-----------------------------| 54 * | | 915 | 965 | ILK | SNB | IVB | 55 * +----------------------------------------------------------------------+ 56 * | YUV 4:2:2 format | 8 | 4 | 4 | 4 | 4 | 57 * | BC1-5 compressed format (DXTn/S3TC) | 4 | 4 | 4 | 4 | 4 | 58 * | FXT1 compressed format | 8 | 8 | 8 | 8 | 8 | 59 * | Depth Buffer (16-bit) | 4 | 4 | 4 | 4 | 8 | 60 * | Depth Buffer (other) | 4 | 4 | 4 | 4 | 4 | 61 * | Separate Stencil Buffer | N/A | N/A | 8 | 8 | 8 | 62 * | All Others | 4 | 4 | 4 | 4 | 4 | 63 * +----------------------------------------------------------------------+ 64 * 65 * On IVB+, non-special cases can be overridden by setting the SURFACE_STATE 66 * "Surface Horizontal Alignment" field to HALIGN_4 or HALIGN_8. 67 */ 68 if (_mesa_is_format_compressed(format)) { 69 /* The hardware alignment requirements for compressed textures 70 * happen to match the block boundaries. 71 */ 72 unsigned int i, j; 73 _mesa_get_format_block_size(format, &i, &j); 74 return i; 75 } 76 77 if (format == MESA_FORMAT_S8) 78 return 8; 79 80 if (intel->gen >= 7 && format == MESA_FORMAT_Z16) 81 return 8; 82 83 return 4; 84 } 85 86 static unsigned int 87 intel_vertical_texture_alignment_unit(struct intel_context *intel, 88 gl_format format) 89 { 90 /** 91 * From the "Alignment Unit Size" section of various specs, namely: 92 * - Gen3 Spec: "Memory Data Formats" Volume, Section 1.20.1.4 93 * - i965 and G45 PRMs: Volume 1, Section 6.17.3.4. 94 * - Ironlake and Sandybridge PRMs: Volume 1, Part 1, Section 7.18.3.4 95 * - BSpec (for Ivybridge and slight variations in separate stencil) 96 * 97 * +----------------------------------------------------------------------+ 98 * | | alignment unit height ("j") | 99 * | Surface Property |-----------------------------| 100 * | | 915 | 965 | ILK | SNB | IVB | 101 * +----------------------------------------------------------------------+ 102 * | BC1-5 compressed format (DXTn/S3TC) | 4 | 4 | 4 | 4 | 4 | 103 * | FXT1 compressed format | 4 | 4 | 4 | 4 | 4 | 104 * | Depth Buffer | 2 | 2 | 2 | 4 | 4 | 105 * | Separate Stencil Buffer | N/A | N/A | N/A | 4 | 8 | 106 * | Multisampled (4x or 8x) render target | N/A | N/A | N/A | 4 | 4 | 107 * | All Others | 2 | 2 | 2 | 2 | 2 | 108 * +----------------------------------------------------------------------+ 109 * 110 * On SNB+, non-special cases can be overridden by setting the SURFACE_STATE 111 * "Surface Vertical Alignment" field to VALIGN_2 or VALIGN_4. 112 * 113 * We currently don't support multisampling. 114 */ 115 if (_mesa_is_format_compressed(format)) 116 return 4; 117 118 if (format == MESA_FORMAT_S8) 119 return intel->gen >= 7 ? 8 : 4; 120 121 GLenum base_format = _mesa_get_format_base_format(format); 122 123 if (intel->gen >= 6 && 124 (base_format == GL_DEPTH_COMPONENT || 125 base_format == GL_DEPTH_STENCIL)) { 126 return 4; 127 } 128 129 return 2; 130 } 131 132 void 133 intel_get_texture_alignment_unit(struct intel_context *intel, 134 gl_format format, 135 unsigned int *w, unsigned int *h) 136 { 137 *w = intel_horizontal_texture_alignment_unit(intel, format); 138 *h = intel_vertical_texture_alignment_unit(intel, format); 139 } 140 141 void i945_miptree_layout_2d(struct intel_mipmap_tree *mt) 142 { 143 GLuint level; 144 GLuint x = 0; 145 GLuint y = 0; 146 GLuint width = mt->width0; 147 GLuint height = mt->height0; 148 GLuint depth = mt->depth0; /* number of array layers. */ 149 150 mt->total_width = mt->width0; 151 152 if (mt->compressed) { 153 mt->total_width = ALIGN(mt->width0, mt->align_w); 154 } 155 156 /* May need to adjust width to accomodate the placement of 157 * the 2nd mipmap. This occurs when the alignment 158 * constraints of mipmap placement push the right edge of the 159 * 2nd mipmap out past the width of its parent. 160 */ 161 if (mt->first_level != mt->last_level) { 162 GLuint mip1_width; 163 164 if (mt->compressed) { 165 mip1_width = ALIGN(minify(mt->width0), mt->align_w) 166 + ALIGN(minify(minify(mt->width0)), mt->align_w); 167 } else { 168 mip1_width = ALIGN(minify(mt->width0), mt->align_w) 169 + minify(minify(mt->width0)); 170 } 171 172 if (mip1_width > mt->total_width) { 173 mt->total_width = mip1_width; 174 } 175 } 176 177 mt->total_height = 0; 178 179 for ( level = mt->first_level ; level <= mt->last_level ; level++ ) { 180 GLuint img_height; 181 182 intel_miptree_set_level_info(mt, level, x, y, width, 183 height, depth); 184 185 img_height = ALIGN(height, mt->align_h); 186 if (mt->compressed) 187 img_height /= mt->align_h; 188 189 /* Because the images are packed better, the final offset 190 * might not be the maximal one: 191 */ 192 mt->total_height = MAX2(mt->total_height, y + img_height); 193 194 /* Layout_below: step right after second mipmap. 195 */ 196 if (level == mt->first_level + 1) { 197 x += ALIGN(width, mt->align_w); 198 } 199 else { 200 y += img_height; 201 } 202 203 width = minify(width); 204 height = minify(height); 205 } 206 } 207
