1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef _ASM_PCI_BRIDGE_H 20 #define _ASM_PCI_BRIDGE_H 21 #include <linux/types.h> 22 #include <linux/pci.h> 23 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 24 #include <asm/xtalk/xwidget.h> 25 #include <asm/sn/types.h> 26 #define IOPFNSHIFT 12 27 #define IOPGSIZE (1 << IOPFNSHIFT) 28 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 29 #define IOPG(x) ((x) >> IOPFNSHIFT) 30 #define IOPGOFF(x) ((x) & (IOPGSIZE-1)) 31 #define BRIDGE_ATE_RAM_SIZE 0x00000400 32 #define BRIDGE_CONFIG_BASE 0x20000 33 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 34 #define BRIDGE_CONFIG1_BASE 0x28000 35 #define BRIDGE_CONFIG_END 0x30000 36 #define BRIDGE_CONFIG_SLOT_SIZE 0x1000 37 #define BRIDGE_SSRAM_512K 0x00080000 38 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39 #define BRIDGE_SSRAM_128K 0x00020000 40 #define BRIDGE_SSRAM_64K 0x00010000 41 #define BRIDGE_SSRAM_0K 0x00000000 42 #ifndef __ASSEMBLY__ 43 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 44 typedef u32 bridgereg_t; 45 typedef u64 bridge_ate_t; 46 typedef volatile bridge_ate_t *bridge_ate_p; 47 typedef volatile struct bridge_s { 48 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 49 widget_cfg_t b_widget; 50 #define b_wid_id b_widget.w_id 51 #define b_wid_stat b_widget.w_status 52 #define b_wid_err_upper b_widget.w_err_upper_addr 53 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 54 #define b_wid_err_lower b_widget.w_err_lower_addr 55 #define b_wid_control b_widget.w_control 56 #define b_wid_req_timeout b_widget.w_req_timeout 57 #define b_wid_int_upper b_widget.w_intdest_upper_addr 58 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 59 #define b_wid_int_lower b_widget.w_intdest_lower_addr 60 #define b_wid_err_cmdword b_widget.w_err_cmd_word 61 #define b_wid_llp b_widget.w_llp_cfg 62 #define b_wid_tflush b_widget.w_tflush 63 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 64 bridgereg_t _pad_000058; 65 bridgereg_t b_wid_aux_err; 66 bridgereg_t _pad_000060; 67 bridgereg_t b_wid_resp_upper; 68 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 69 bridgereg_t _pad_000068; 70 bridgereg_t b_wid_resp_lower; 71 bridgereg_t _pad_000070; 72 bridgereg_t b_wid_tst_pin_ctrl; 73 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 74 bridgereg_t _pad_000078[2]; 75 bridgereg_t _pad_000080; 76 bridgereg_t b_dir_map; 77 bridgereg_t _pad_000088[2]; 78 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 79 bridgereg_t _pad_000090; 80 bridgereg_t b_ram_perr; 81 bridgereg_t _pad_000098[2]; 82 bridgereg_t _pad_0000A0; 83 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 84 bridgereg_t b_arb; 85 bridgereg_t _pad_0000A8[2]; 86 bridgereg_t _pad_0000B0; 87 bridgereg_t b_nic; 88 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 89 bridgereg_t _pad_0000B8[2]; 90 bridgereg_t _pad_0000C0; 91 bridgereg_t b_bus_timeout; 92 #define b_pci_bus_timeout b_bus_timeout 93 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 94 bridgereg_t _pad_0000C8; 95 bridgereg_t b_pci_cfg; 96 bridgereg_t _pad_0000D0; 97 bridgereg_t b_pci_err_upper; 98 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 99 bridgereg_t _pad_0000D8; 100 bridgereg_t b_pci_err_lower; 101 bridgereg_t _pad_0000E0[8]; 102 #define b_gio_err_lower b_pci_err_lower 103 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 104 #define b_gio_err_upper b_pci_err_upper 105 bridgereg_t _pad_000100; 106 bridgereg_t b_int_status; 107 bridgereg_t _pad_000108; 108 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 109 bridgereg_t b_int_enable; 110 bridgereg_t _pad_000110; 111 bridgereg_t b_int_rst_stat; 112 bridgereg_t _pad_000118; 113 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 114 bridgereg_t b_int_mode; 115 bridgereg_t _pad_000120; 116 bridgereg_t b_int_device; 117 bridgereg_t _pad_000128; 118 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 119 bridgereg_t b_int_host_err; 120 struct { 121 bridgereg_t __pad; 122 bridgereg_t addr; 123 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 124 } b_int_addr[8]; 125 bridgereg_t _pad_000170[36]; 126 struct { 127 bridgereg_t __pad; 128 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 129 bridgereg_t reg; 130 } b_device[8]; 131 struct { 132 bridgereg_t __pad; 133 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 134 bridgereg_t reg; 135 } b_wr_req_buf[8]; 136 struct { 137 bridgereg_t __pad; 138 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 139 bridgereg_t reg; 140 } b_rrb_map[2]; 141 #define b_even_resp b_rrb_map[0].reg 142 #define b_odd_resp b_rrb_map[1].reg 143 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 144 bridgereg_t _pad_000290; 145 bridgereg_t b_resp_status; 146 bridgereg_t _pad_000298; 147 bridgereg_t b_resp_clear; 148 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 149 bridgereg_t _pad_0002A0[24]; 150 char _pad_000300[0x10000 - 0x000300]; 151 union { 152 bridge_ate_t wr; 153 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 154 struct { 155 bridgereg_t _p_pad; 156 bridgereg_t rd; 157 } hi; 158 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 159 } b_int_ate_ram[128]; 160 char _pad_010400[0x11000 - 0x010400]; 161 struct { 162 bridgereg_t _p_pad; 163 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 164 bridgereg_t rd; 165 } b_int_ate_ram_lo[128]; 166 char _pad_011400[0x20000 - 0x011400]; 167 union { 168 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 169 u8 c[0x1000 / 1]; 170 u16 s[0x1000 / 2]; 171 u32 l[0x1000 / 4]; 172 u64 d[0x1000 / 8]; 173 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 174 union { 175 u8 c[0x100 / 1]; 176 u16 s[0x100 / 2]; 177 u32 l[0x100 / 4]; 178 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 179 u64 d[0x100 / 8]; 180 } f[8]; 181 } b_type0_cfg_dev[8]; 182 union { 183 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 184 u8 c[0x1000 / 1]; 185 u16 s[0x1000 / 2]; 186 u32 l[0x1000 / 4]; 187 u64 d[0x1000 / 8]; 188 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 189 } b_type1_cfg; 190 char _pad_029000[0x007000]; 191 union { 192 u8 c[8 / 1]; 193 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 194 u16 s[8 / 2]; 195 u32 l[8 / 4]; 196 u64 d[8 / 8]; 197 } b_pci_iack; 198 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 199 u8 _pad_030007[0x04fff8]; 200 bridge_ate_t b_ext_ate_ram[0x10000]; 201 char _pad_100000[0x200000-0x100000]; 202 union { 203 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 204 u8 c[0x100000 / 1]; 205 u16 s[0x100000 / 2]; 206 u32 l[0x100000 / 4]; 207 u64 d[0x100000 / 8]; 208 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 209 } b_devio_raw[10]; 210 #define b_devio(n) b_devio_raw[((n)<2)?(n*2):(n+2)] 211 union { 212 u8 c[0x400000 / 1]; 213 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 214 u16 s[0x400000 / 2]; 215 u32 l[0x400000 / 4]; 216 u64 d[0x400000 / 8]; 217 } b_external_flash; 218 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 219 } bridge_t; 220 typedef struct bridge_err_cmdword_s { 221 union { 222 u32 cmd_word; 223 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 224 struct { 225 u32 didn:4, 226 sidn:4, 227 pactyp:4, 228 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 229 tnum:5, 230 coh:1, 231 ds:2, 232 gbr:1, 233 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 234 vbpm:1, 235 error:1, 236 barr:1, 237 rsvd:8; 238 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 239 } berr_st; 240 } berr_un; 241 } bridge_err_cmdword_t; 242 #define berr_field berr_un.berr_st 243 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 244 #endif 245 #define BRIDGE_WID_ID WIDGET_ID 246 #define BRIDGE_WID_STAT WIDGET_STATUS 247 #define BRIDGE_WID_ERR_UPPER WIDGET_ERR_UPPER_ADDR 248 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 249 #define BRIDGE_WID_ERR_LOWER WIDGET_ERR_LOWER_ADDR 250 #define BRIDGE_WID_CONTROL WIDGET_CONTROL 251 #define BRIDGE_WID_REQ_TIMEOUT WIDGET_REQ_TIMEOUT 252 #define BRIDGE_WID_INT_UPPER WIDGET_INTDEST_UPPER_ADDR 253 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 254 #define BRIDGE_WID_INT_LOWER WIDGET_INTDEST_LOWER_ADDR 255 #define BRIDGE_WID_ERR_CMDWORD WIDGET_ERR_CMD_WORD 256 #define BRIDGE_WID_LLP WIDGET_LLP_CFG 257 #define BRIDGE_WID_TFLUSH WIDGET_TFLUSH 258 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 259 #define BRIDGE_WID_AUX_ERR 0x00005C 260 #define BRIDGE_WID_RESP_UPPER 0x000064 261 #define BRIDGE_WID_RESP_LOWER 0x00006C 262 #define BRIDGE_WID_TST_PIN_CTRL 0x000074 263 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 264 #define BRIDGE_DIR_MAP 0x000084 265 #define BRIDGE_RAM_PERR 0x000094 266 #define BRIDGE_ARB 0x0000A4 267 #define BRIDGE_NIC 0x0000B4 268 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 269 #define BRIDGE_BUS_TIMEOUT 0x0000C4 270 #define BRIDGE_PCI_BUS_TIMEOUT BRIDGE_BUS_TIMEOUT 271 #define BRIDGE_PCI_CFG 0x0000CC 272 #define BRIDGE_PCI_ERR_UPPER 0x0000D4 273 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 274 #define BRIDGE_PCI_ERR_LOWER 0x0000DC 275 #define BRIDGE_INT_STATUS 0x000104 276 #define BRIDGE_INT_ENABLE 0x00010C 277 #define BRIDGE_INT_RST_STAT 0x000114 278 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 279 #define BRIDGE_INT_MODE 0x00011C 280 #define BRIDGE_INT_DEVICE 0x000124 281 #define BRIDGE_INT_HOST_ERR 0x00012C 282 #define BRIDGE_INT_ADDR0 0x000134 283 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 284 #define BRIDGE_INT_ADDR_OFF 0x000008 285 #define BRIDGE_INT_ADDR(x) (BRIDGE_INT_ADDR0+(x)*BRIDGE_INT_ADDR_OFF) 286 #define BRIDGE_DEVICE0 0x000204 287 #define BRIDGE_DEVICE_OFF 0x000008 288 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 289 #define BRIDGE_DEVICE(x) (BRIDGE_DEVICE0+(x)*BRIDGE_DEVICE_OFF) 290 #define BRIDGE_WR_REQ_BUF0 0x000244 291 #define BRIDGE_WR_REQ_BUF_OFF 0x000008 292 #define BRIDGE_WR_REQ_BUF(x) (BRIDGE_WR_REQ_BUF0+(x)*BRIDGE_WR_REQ_BUF_OFF) 293 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 294 #define BRIDGE_EVEN_RESP 0x000284 295 #define BRIDGE_ODD_RESP 0x00028C 296 #define BRIDGE_RESP_STATUS 0x000294 297 #define BRIDGE_RESP_CLEAR 0x00029C 298 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 299 #define BRIDGE_ATE_RAM 0x00010000 300 #define BRIDGE_TYPE0_CFG_DEV0 0x00020000 301 #define BRIDGE_TYPE0_CFG_SLOT_OFF 0x00001000 302 #define BRIDGE_TYPE0_CFG_FUNC_OFF 0x00000100 303 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 304 #define BRIDGE_TYPE0_CFG_DEV(s) (BRIDGE_TYPE0_CFG_DEV0+ (s)*BRIDGE_TYPE0_CFG_SLOT_OFF) 305 #define BRIDGE_TYPE0_CFG_DEVF(s, f) (BRIDGE_TYPE0_CFG_DEV0+ (s)*BRIDGE_TYPE0_CFG_SLOT_OFF+ (f)*BRIDGE_TYPE0_CFG_FUNC_OFF) 306 #define BRIDGE_TYPE1_CFG 0x00028000 307 #define BRIDGE_PCI_IACK 0x00030000 308 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 309 #define BRIDGE_EXT_SSRAM 0x00080000 310 #define BRIDGE_DEV_CNT 8 311 #define BRIDGE_DEVIO0 0x00200000 312 #define BRIDGE_DEVIO1 0x00400000 313 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 314 #define BRIDGE_DEVIO2 0x00600000 315 #define BRIDGE_DEVIO_OFF 0x00100000 316 #define BRIDGE_DEVIO_2MB 0x00200000 317 #define BRIDGE_DEVIO_1MB 0x00100000 318 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 319 #define BRIDGE_DEVIO(x) ((x)<=1 ? BRIDGE_DEVIO0+(x)*BRIDGE_DEVIO_2MB : BRIDGE_DEVIO2+((x)-2)*BRIDGE_DEVIO_1MB) 320 #define BRIDGE_EXTERNAL_FLASH 0x00C00000 321 #define BRIDGE_WIDGET_PART_NUM 0xc002 322 #define XBRIDGE_WIDGET_PART_NUM 0xd002 323 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 324 #define BRIDGE_WIDGET_MFGR_NUM 0x036 325 #define XBRIDGE_WIDGET_MFGR_NUM 0x024 326 #define BRIDGE_REV_A 0x1 327 #define BRIDGE_REV_B 0x2 328 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 329 #define BRIDGE_REV_C 0x3 330 #define BRIDGE_REV_D 0x4 331 #define BRIDGE_STAT_LLP_REC_CNT (0xFFu << 24) 332 #define BRIDGE_STAT_LLP_TX_CNT (0xFF << 16) 333 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 334 #define BRIDGE_STAT_FLASH_SELECT (0x1 << 6) 335 #define BRIDGE_STAT_PCI_GIO_N (0x1 << 5) 336 #define BRIDGE_STAT_PENDING (0x1F << 0) 337 #define BRIDGE_CTRL_FLASH_WR_EN (0x1ul << 31) 338 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 339 #define BRIDGE_CTRL_EN_CLK50 (0x1 << 30) 340 #define BRIDGE_CTRL_EN_CLK40 (0x1 << 29) 341 #define BRIDGE_CTRL_EN_CLK33 (0x1 << 28) 342 #define BRIDGE_CTRL_RST(n) ((n) << 24) 343 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 344 #define BRIDGE_CTRL_RST_MASK (BRIDGE_CTRL_RST(0xF)) 345 #define BRIDGE_CTRL_RST_PIN(x) (BRIDGE_CTRL_RST(0x1 << (x))) 346 #define BRIDGE_CTRL_IO_SWAP (0x1 << 23) 347 #define BRIDGE_CTRL_MEM_SWAP (0x1 << 22) 348 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 349 #define BRIDGE_CTRL_PAGE_SIZE (0x1 << 21) 350 #define BRIDGE_CTRL_SS_PAR_BAD (0x1 << 20) 351 #define BRIDGE_CTRL_SS_PAR_EN (0x1 << 19) 352 #define BRIDGE_CTRL_SSRAM_SIZE(n) ((n) << 17) 353 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 354 #define BRIDGE_CTRL_SSRAM_SIZE_MASK (BRIDGE_CTRL_SSRAM_SIZE(0x3)) 355 #define BRIDGE_CTRL_SSRAM_512K (BRIDGE_CTRL_SSRAM_SIZE(0x3)) 356 #define BRIDGE_CTRL_SSRAM_128K (BRIDGE_CTRL_SSRAM_SIZE(0x2)) 357 #define BRIDGE_CTRL_SSRAM_64K (BRIDGE_CTRL_SSRAM_SIZE(0x1)) 358 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 359 #define BRIDGE_CTRL_SSRAM_1K (BRIDGE_CTRL_SSRAM_SIZE(0x0)) 360 #define BRIDGE_CTRL_F_BAD_PKT (0x1 << 16) 361 #define BRIDGE_CTRL_LLP_XBAR_CRD(n) ((n) << 12) 362 #define BRIDGE_CTRL_LLP_XBAR_CRD_MASK (BRIDGE_CTRL_LLP_XBAR_CRD(0xf)) 363 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 364 #define BRIDGE_CTRL_CLR_RLLP_CNT (0x1 << 11) 365 #define BRIDGE_CTRL_CLR_TLLP_CNT (0x1 << 10) 366 #define BRIDGE_CTRL_SYS_END (0x1 << 9) 367 #define BRIDGE_CTRL_MAX_TRANS(n) ((n) << 4) 368 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 369 #define BRIDGE_CTRL_MAX_TRANS_MASK (BRIDGE_CTRL_MAX_TRANS(0x1f)) 370 #define BRIDGE_CTRL_WIDGET_ID(n) ((n) << 0) 371 #define BRIDGE_CTRL_WIDGET_ID_MASK (BRIDGE_CTRL_WIDGET_ID(0xf)) 372 #define BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT (20) 373 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 374 #define BRIDGE_RESP_ERRUPPR_DEVNUM_MASK (0x7 << BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT) 375 #define BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT (16) 376 #define BRIDGE_RESP_ERRUPPR_BUFNUM_MASK (0xF << BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT) 377 #define BRIDGE_RESP_ERRRUPPR_BUFMASK (0xFFFF) 378 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 379 #define BRIDGE_RESP_ERRUPPR_BUFNUM(x) (((x) & BRIDGE_RESP_ERRUPPR_BUFNUM_MASK) >> BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT) 380 #define BRIDGE_RESP_ERRUPPR_DEVICE(x) (((x) & BRIDGE_RESP_ERRUPPR_DEVNUM_MASK) >> BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT) 381 #define BRIDGE_DIRMAP_W_ID_SHFT 20 382 #define BRIDGE_DIRMAP_W_ID (0xf << BRIDGE_DIRMAP_W_ID_SHFT) 383 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 384 #define BRIDGE_DIRMAP_RMF_64 (0x1 << 18) 385 #define BRIDGE_DIRMAP_ADD512 (0x1 << 17) 386 #define BRIDGE_DIRMAP_OFF (0x1ffff << 0) 387 #define BRIDGE_DIRMAP_OFF_ADDRSHFT (31) 388 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 389 #define BRIDGE_ARB_REQ_WAIT_TICK(x) ((x) << 16) 390 #define BRIDGE_ARB_REQ_WAIT_TICK_MASK BRIDGE_ARB_REQ_WAIT_TICK(0x3) 391 #define BRIDGE_ARB_REQ_WAIT_EN(x) ((x) << 8) 392 #define BRIDGE_ARB_REQ_WAIT_EN_MASK BRIDGE_ARB_REQ_WAIT_EN(0xff) 393 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 394 #define BRIDGE_ARB_FREEZE_GNT (1 << 6) 395 #define BRIDGE_ARB_HPRI_RING_B2 (1 << 5) 396 #define BRIDGE_ARB_HPRI_RING_B1 (1 << 4) 397 #define BRIDGE_ARB_HPRI_RING_B0 (1 << 3) 398 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 399 #define BRIDGE_ARB_LPRI_RING_B2 (1 << 2) 400 #define BRIDGE_ARB_LPRI_RING_B1 (1 << 1) 401 #define BRIDGE_ARB_LPRI_RING_B0 (1 << 0) 402 #define BRIDGE_BUS_PCI_RETRY_HLD(x) ((x) << 16) 403 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 404 #define BRIDGE_BUS_PCI_RETRY_HLD_MASK BRIDGE_BUS_PCI_RETRY_HLD(0x1f) 405 #define BRIDGE_BUS_GIO_TIMEOUT (1 << 12) 406 #define BRIDGE_BUS_PCI_RETRY_CNT(x) ((x) << 0) 407 #define BRIDGE_BUS_PCI_RETRY_MASK BRIDGE_BUS_PCI_RETRY_CNT(0x3ff) 408 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 409 #define BRIDGE_ISR_MULTI_ERR (0x1u << 31) 410 #define BRIDGE_ISR_PMU_ESIZE_FAULT (0x1 << 30) 411 #define BRIDGE_ISR_UNEXP_RESP (0x1 << 29) 412 #define BRIDGE_ISR_BAD_XRESP_PKT (0x1 << 28) 413 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 414 #define BRIDGE_ISR_BAD_XREQ_PKT (0x1 << 27) 415 #define BRIDGE_ISR_RESP_XTLK_ERR (0x1 << 26) 416 #define BRIDGE_ISR_REQ_XTLK_ERR (0x1 << 25) 417 #define BRIDGE_ISR_INVLD_ADDR (0x1 << 24) 418 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 419 #define BRIDGE_ISR_UNSUPPORTED_XOP (0x1 << 23) 420 #define BRIDGE_ISR_XREQ_FIFO_OFLOW (0x1 << 22) 421 #define BRIDGE_ISR_LLP_REC_SNERR (0x1 << 21) 422 #define BRIDGE_ISR_LLP_REC_CBERR (0x1 << 20) 423 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 424 #define BRIDGE_ISR_LLP_RCTY (0x1 << 19) 425 #define BRIDGE_ISR_LLP_TX_RETRY (0x1 << 18) 426 #define BRIDGE_ISR_LLP_TCTY (0x1 << 17) 427 #define BRIDGE_ISR_SSRAM_PERR (0x1 << 16) 428 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 429 #define BRIDGE_ISR_PCI_ABORT (0x1 << 15) 430 #define BRIDGE_ISR_PCI_PARITY (0x1 << 14) 431 #define BRIDGE_ISR_PCI_SERR (0x1 << 13) 432 #define BRIDGE_ISR_PCI_PERR (0x1 << 12) 433 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 434 #define BRIDGE_ISR_PCI_MST_TIMEOUT (0x1 << 11) 435 #define BRIDGE_ISR_GIO_MST_TIMEOUT BRIDGE_ISR_PCI_MST_TIMEOUT 436 #define BRIDGE_ISR_PCI_RETRY_CNT (0x1 << 10) 437 #define BRIDGE_ISR_XREAD_REQ_TIMEOUT (0x1 << 9) 438 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 439 #define BRIDGE_ISR_GIO_B_ENBL_ERR (0x1 << 8) 440 #define BRIDGE_ISR_INT_MSK (0xff << 0) 441 #define BRIDGE_ISR_INT(x) (0x1 << (x)) 442 #define BRIDGE_ISR_LINK_ERROR (BRIDGE_ISR_LLP_REC_SNERR|BRIDGE_ISR_LLP_REC_CBERR| BRIDGE_ISR_LLP_RCTY|BRIDGE_ISR_LLP_TX_RETRY| BRIDGE_ISR_LLP_TCTY) 443 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 444 #define BRIDGE_ISR_PCIBUS_PIOERR (BRIDGE_ISR_PCI_MST_TIMEOUT|BRIDGE_ISR_PCI_ABORT) 445 #define BRIDGE_ISR_PCIBUS_ERROR (BRIDGE_ISR_PCIBUS_PIOERR|BRIDGE_ISR_PCI_PERR| BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_RETRY_CNT| BRIDGE_ISR_PCI_PARITY) 446 #define BRIDGE_ISR_XTALK_ERROR (BRIDGE_ISR_XREAD_REQ_TIMEOUT|BRIDGE_ISR_XREQ_FIFO_OFLOW| BRIDGE_ISR_UNSUPPORTED_XOP|BRIDGE_ISR_INVLD_ADDR| BRIDGE_ISR_REQ_XTLK_ERR|BRIDGE_ISR_RESP_XTLK_ERR| BRIDGE_ISR_BAD_XREQ_PKT|BRIDGE_ISR_BAD_XRESP_PKT| BRIDGE_ISR_UNEXP_RESP) 447 #define BRIDGE_ISR_ERRORS (BRIDGE_ISR_LINK_ERROR|BRIDGE_ISR_PCIBUS_ERROR| BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR| BRIDGE_ISR_PMU_ESIZE_FAULT) 448 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 449 #define BRIDGE_ISR_ERROR_FATAL ((BRIDGE_ISR_XTALK_ERROR & ~BRIDGE_ISR_XREAD_REQ_TIMEOUT)| BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_PARITY ) 450 #define BRIDGE_ISR_ERROR_DUMP (BRIDGE_ISR_PCIBUS_ERROR|BRIDGE_ISR_PMU_ESIZE_FAULT| BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR) 451 #define BRIDGE_IMR_UNEXP_RESP BRIDGE_ISR_UNEXP_RESP 452 #define BRIDGE_IMR_PMU_ESIZE_FAULT BRIDGE_ISR_PMU_ESIZE_FAULT 453 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 454 #define BRIDGE_IMR_BAD_XRESP_PKT BRIDGE_ISR_BAD_XRESP_PKT 455 #define BRIDGE_IMR_BAD_XREQ_PKT BRIDGE_ISR_BAD_XREQ_PKT 456 #define BRIDGE_IMR_RESP_XTLK_ERR BRIDGE_ISR_RESP_XTLK_ERR 457 #define BRIDGE_IMR_REQ_XTLK_ERR BRIDGE_ISR_REQ_XTLK_ERR 458 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 459 #define BRIDGE_IMR_INVLD_ADDR BRIDGE_ISR_INVLD_ADDR 460 #define BRIDGE_IMR_UNSUPPORTED_XOP BRIDGE_ISR_UNSUPPORTED_XOP 461 #define BRIDGE_IMR_XREQ_FIFO_OFLOW BRIDGE_ISR_XREQ_FIFO_OFLOW 462 #define BRIDGE_IMR_LLP_REC_SNERR BRIDGE_ISR_LLP_REC_SNERR 463 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 464 #define BRIDGE_IMR_LLP_REC_CBERR BRIDGE_ISR_LLP_REC_CBERR 465 #define BRIDGE_IMR_LLP_RCTY BRIDGE_ISR_LLP_RCTY 466 #define BRIDGE_IMR_LLP_TX_RETRY BRIDGE_ISR_LLP_TX_RETRY 467 #define BRIDGE_IMR_LLP_TCTY BRIDGE_ISR_LLP_TCTY 468 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 469 #define BRIDGE_IMR_SSRAM_PERR BRIDGE_ISR_SSRAM_PERR 470 #define BRIDGE_IMR_PCI_ABORT BRIDGE_ISR_PCI_ABORT 471 #define BRIDGE_IMR_PCI_PARITY BRIDGE_ISR_PCI_PARITY 472 #define BRIDGE_IMR_PCI_SERR BRIDGE_ISR_PCI_SERR 473 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 474 #define BRIDGE_IMR_PCI_PERR BRIDGE_ISR_PCI_PERR 475 #define BRIDGE_IMR_PCI_MST_TIMEOUT BRIDGE_ISR_PCI_MST_TIMEOUT 476 #define BRIDGE_IMR_GIO_MST_TIMEOUT BRIDGE_ISR_GIO_MST_TIMEOUT 477 #define BRIDGE_IMR_PCI_RETRY_CNT BRIDGE_ISR_PCI_RETRY_CNT 478 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 479 #define BRIDGE_IMR_XREAD_REQ_TIMEOUT BRIDGE_ISR_XREAD_REQ_TIMEOUT 480 #define BRIDGE_IMR_GIO_B_ENBL_ERR BRIDGE_ISR_GIO_B_ENBL_ERR 481 #define BRIDGE_IMR_INT_MSK BRIDGE_ISR_INT_MSK 482 #define BRIDGE_IMR_INT(x) BRIDGE_ISR_INT(x) 483 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 484 #define BRIDGE_IRR_MULTI_CLR (0x1 << 6) 485 #define BRIDGE_IRR_CRP_GRP_CLR (0x1 << 5) 486 #define BRIDGE_IRR_RESP_BUF_GRP_CLR (0x1 << 4) 487 #define BRIDGE_IRR_REQ_DSP_GRP_CLR (0x1 << 3) 488 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 489 #define BRIDGE_IRR_LLP_GRP_CLR (0x1 << 2) 490 #define BRIDGE_IRR_SSRAM_GRP_CLR (0x1 << 1) 491 #define BRIDGE_IRR_PCI_GRP_CLR (0x1 << 0) 492 #define BRIDGE_IRR_GIO_GRP_CLR (0x1 << 0) 493 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 494 #define BRIDGE_IRR_ALL_CLR 0x7f 495 #define BRIDGE_IRR_CRP_GRP (BRIDGE_ISR_UNEXP_RESP | BRIDGE_ISR_XREQ_FIFO_OFLOW) 496 #define BRIDGE_IRR_RESP_BUF_GRP (BRIDGE_ISR_BAD_XRESP_PKT | BRIDGE_ISR_RESP_XTLK_ERR | BRIDGE_ISR_XREAD_REQ_TIMEOUT) 497 #define BRIDGE_IRR_REQ_DSP_GRP (BRIDGE_ISR_UNSUPPORTED_XOP | BRIDGE_ISR_BAD_XREQ_PKT | BRIDGE_ISR_REQ_XTLK_ERR | BRIDGE_ISR_INVLD_ADDR) 498 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 499 #define BRIDGE_IRR_LLP_GRP (BRIDGE_ISR_LLP_REC_SNERR | BRIDGE_ISR_LLP_REC_CBERR | BRIDGE_ISR_LLP_RCTY | BRIDGE_ISR_LLP_TX_RETRY | BRIDGE_ISR_LLP_TCTY) 500 #define BRIDGE_IRR_SSRAM_GRP (BRIDGE_ISR_SSRAM_PERR | BRIDGE_ISR_PMU_ESIZE_FAULT) 501 #define BRIDGE_IRR_PCI_GRP (BRIDGE_ISR_PCI_ABORT | BRIDGE_ISR_PCI_PARITY | BRIDGE_ISR_PCI_SERR | BRIDGE_ISR_PCI_PERR | BRIDGE_ISR_PCI_MST_TIMEOUT | BRIDGE_ISR_PCI_RETRY_CNT) 502 #define BRIDGE_IRR_GIO_GRP (BRIDGE_ISR_GIO_B_ENBL_ERR | BRIDGE_ISR_GIO_MST_TIMEOUT) 503 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 504 #define BRIDGE_INT_DEV_SHFT(n) ((n)*3) 505 #define BRIDGE_INT_DEV_MASK(n) (0x7 << BRIDGE_INT_DEV_SHFT(n)) 506 #define BRIDGE_INT_DEV_SET(_dev, _line) (_dev << BRIDGE_INT_DEV_SHFT(_line)) 507 #define BRIDGE_INT_ADDR_HOST 0x0003FF00 508 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 509 #define BRIDGE_INT_ADDR_FLD 0x000000FF 510 #define BRIDGE_TMO_PCI_RETRY_HLD_MASK 0x1f0000 511 #define BRIDGE_TMO_GIO_TIMEOUT_MASK 0x001000 512 #define BRIDGE_TMO_PCI_RETRY_CNT_MASK 0x0003ff 513 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 514 #define BRIDGE_TMO_PCI_RETRY_CNT_MAX 0x3ff 515 #define BRIDGE_INT_ADDR_NASID_SHFT 8 516 #define BRIDGE_INT_ADDR_DEST_IO (1 << 17) 517 #define BRIDGE_INT_ADDR_DEST_MEM 0 518 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 519 #define BRIDGE_INT_ADDR_MASK (1 << 17) 520 #define BRIDGE_DEV_ERR_LOCK_EN 0x10000000 521 #define BRIDGE_DEV_PAGE_CHK_DIS 0x08000000 522 #define BRIDGE_DEV_FORCE_PCI_PAR 0x04000000 523 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 524 #define BRIDGE_DEV_VIRTUAL_EN 0x02000000 525 #define BRIDGE_DEV_PMU_WRGA_EN 0x01000000 526 #define BRIDGE_DEV_DIR_WRGA_EN 0x00800000 527 #define BRIDGE_DEV_DEV_SIZE 0x00400000 528 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 529 #define BRIDGE_DEV_RT 0x00200000 530 #define BRIDGE_DEV_SWAP_PMU 0x00100000 531 #define BRIDGE_DEV_SWAP_DIR 0x00080000 532 #define BRIDGE_DEV_PREF 0x00040000 533 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 534 #define BRIDGE_DEV_PRECISE 0x00020000 535 #define BRIDGE_DEV_COH 0x00010000 536 #define BRIDGE_DEV_BARRIER 0x00008000 537 #define BRIDGE_DEV_GBR 0x00004000 538 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 539 #define BRIDGE_DEV_DEV_SWAP 0x00002000 540 #define BRIDGE_DEV_DEV_IO_MEM 0x00001000 541 #define BRIDGE_DEV_OFF_MASK 0x00000fff 542 #define BRIDGE_DEV_OFF_ADDR_SHFT 20 543 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 544 #define BRIDGE_DEV_PMU_BITS (BRIDGE_DEV_PMU_WRGA_EN | BRIDGE_DEV_SWAP_PMU) 545 #define BRIDGE_DEV_D32_BITS (BRIDGE_DEV_DIR_WRGA_EN | BRIDGE_DEV_SWAP_DIR | BRIDGE_DEV_PREF | BRIDGE_DEV_PRECISE | BRIDGE_DEV_COH | BRIDGE_DEV_BARRIER) 546 #define BRIDGE_DEV_D64_BITS (BRIDGE_DEV_DIR_WRGA_EN | BRIDGE_DEV_SWAP_DIR | BRIDGE_DEV_COH | BRIDGE_DEV_BARRIER) 547 #define BRIDGE_ERRUPPR_DEVMASTER (0x1 << 20) 548 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 549 #define BRIDGE_ERRUPPR_PCIVDEV (0x1 << 19) 550 #define BRIDGE_ERRUPPR_DEVNUM_SHFT (16) 551 #define BRIDGE_ERRUPPR_DEVNUM_MASK (0x7 << BRIDGE_ERRUPPR_DEVNUM_SHFT) 552 #define BRIDGE_ERRUPPR_DEVICE(err) (((err) >> BRIDGE_ERRUPPR_DEVNUM_SHFT) & 0x7) 553 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 554 #define BRIDGE_ERRUPPR_ADDRMASK (0xFFFF) 555 #define BRIDGE_INTMODE_CLR_PKT_EN(x) (0x1 << (x)) 556 #define BRIDGE_CREDIT 3 557 #define BRIDGE_RRB_EN 0x8 558 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 559 #define BRIDGE_RRB_DEV 0x7 560 #define BRIDGE_RRB_VDEV 0x4 561 #define BRIDGE_RRB_PDEV 0x3 562 #define BRIDGE_RRB_VALID(r) (0x00010000<<(r)) 563 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 564 #define BRIDGE_RRB_INUSE(r) (0x00000001<<(r)) 565 #define BRIDGE_RRB_CLEAR(r) (0x00000001<<(r)) 566 #define XBOX_BRIDGE_WID 8 567 #define FLASH_PROM1_BASE 0xE00000 568 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 569 #define XBOX_RPS_EXISTS 1 << 6 570 #define XBOX_RPS_FAIL 1 << 4 571 #define BRIDGE_PIO32_XTALK_ALIAS_BASE 0x000040000000L 572 #define BRIDGE_PIO32_XTALK_ALIAS_LIMIT 0x00007FFFFFFFL 573 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 574 #define BRIDGE_PIO64_XTALK_ALIAS_BASE 0x000080000000L 575 #define BRIDGE_PIO64_XTALK_ALIAS_LIMIT 0x0000BFFFFFFFL 576 #define BRIDGE_PCIIO_XTALK_ALIAS_BASE 0x000100000000L 577 #define BRIDGE_PCIIO_XTALK_ALIAS_LIMIT 0x0001FFFFFFFFL 578 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 579 #define BRIDGE_MIN_PIO_ADDR_MEM 0x00000000 580 #define BRIDGE_MAX_PIO_ADDR_MEM 0x3fffffff 581 #define BRIDGE_MIN_PIO_ADDR_IO 0x00000000 582 #define BRIDGE_MAX_PIO_ADDR_IO 0xffffffff 583 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 584 #define BRIDGE_PCI_MEM32_BASE BRIDGE_PIO32_XTALK_ALIAS_BASE 585 #define BRIDGE_PCI_MEM32_LIMIT BRIDGE_PIO32_XTALK_ALIAS_LIMIT 586 #define BRIDGE_PCI_MEM64_BASE BRIDGE_PIO64_XTALK_ALIAS_BASE 587 #define BRIDGE_PCI_MEM64_LIMIT BRIDGE_PIO64_XTALK_ALIAS_LIMIT 588 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 589 #define BRIDGE_PCI_IO_BASE BRIDGE_PCIIO_XTALK_ALIAS_BASE 590 #define BRIDGE_PCI_IO_LIMIT BRIDGE_PCIIO_XTALK_ALIAS_LIMIT 591 #define BRIDGE_LOCAL_BASE 0 592 #define BRIDGE_DMA_MAPPED_BASE 0x40000000 593 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 594 #define BRIDGE_DMA_MAPPED_SIZE 0x40000000 595 #define BRIDGE_DMA_DIRECT_BASE 0x80000000 596 #define BRIDGE_DMA_DIRECT_SIZE 0x80000000 597 #define PCI32_LOCAL_BASE BRIDGE_LOCAL_BASE 598 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 599 #define PCI32_MAPPED_BASE BRIDGE_DMA_MAPPED_BASE 600 #define PCI32_DIRECT_BASE BRIDGE_DMA_DIRECT_BASE 601 #define IS_PCI32_LOCAL(x) ((ulong_t)(x) < PCI32_MAPPED_BASE) 602 #define IS_PCI32_MAPPED(x) ((ulong_t)(x) < PCI32_DIRECT_BASE && (ulong_t)(x) >= PCI32_MAPPED_BASE) 603 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 604 #define IS_PCI32_DIRECT(x) ((ulong_t)(x) >= PCI32_MAPPED_BASE) 605 #define IS_PCI64(x) ((ulong_t)(x) >= PCI64_BASE) 606 #define BRIDGE_GIO_MEM32_BASE BRIDGE_PIO32_XTALK_ALIAS_BASE 607 #define BRIDGE_GIO_MEM32_LIMIT BRIDGE_PIO32_XTALK_ALIAS_LIMIT 608 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 609 #define GIO_LOCAL_BASE BRIDGE_LOCAL_BASE 610 #define GIO_MAPPED_BASE BRIDGE_DMA_MAPPED_BASE 611 #define GIO_DIRECT_BASE BRIDGE_DMA_DIRECT_BASE 612 #define IS_GIO_LOCAL(x) ((ulong_t)(x) < GIO_MAPPED_BASE) 613 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 614 #define IS_GIO_MAPPED(x) ((ulong_t)(x) < GIO_DIRECT_BASE && (ulong_t)(x) >= GIO_MAPPED_BASE) 615 #define IS_GIO_DIRECT(x) ((ulong_t)(x) >= GIO_MAPPED_BASE) 616 #define BRIDGE_DIRECT_32_SEG_SIZE BRIDGE_DMA_DIRECT_SIZE 617 #define BRIDGE_DIRECT_32_TO_XTALK(dir_off,adr) ((dir_off) * BRIDGE_DIRECT_32_SEG_SIZE + ((adr) & (BRIDGE_DIRECT_32_SEG_SIZE - 1)) + PHYS_RAMBASE) 618 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 619 #define PCI64_ATTR_TARG_MASK 0xf000000000000000 620 #define PCI64_ATTR_TARG_SHFT 60 621 #define PCI64_ATTR_PREF 0x0800000000000000 622 #define PCI64_ATTR_PREC 0x0400000000000000 623 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 624 #define PCI64_ATTR_VIRTUAL 0x0200000000000000 625 #define PCI64_ATTR_BAR 0x0100000000000000 626 #define PCI64_ATTR_RMF_MASK 0x00ff000000000000 627 #define PCI64_ATTR_RMF_SHFT 48 628 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 629 #ifndef __ASSEMBLY__ 630 typedef union ate_u { 631 u64 ent; 632 struct ate_s { 633 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 634 u64 rmf:16; 635 u64 addr:36; 636 u64 targ:4; 637 u64 reserved:3; 638 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 639 u64 barrier:1; 640 u64 prefetch:1; 641 u64 precise:1; 642 u64 coherent:1; 643 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 644 u64 valid:1; 645 } field; 646 } ate_t; 647 #endif 648 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 649 #define ATE_V 0x01 650 #define ATE_CO 0x02 651 #define ATE_PREC 0x04 652 #define ATE_PREF 0x08 653 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 654 #define ATE_BAR 0x10 655 #define ATE_PFNSHIFT 12 656 #define ATE_TIDSHIFT 8 657 #define ATE_RMFSHIFT 48 658 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 659 #define mkate(xaddr, xid, attr) ((xaddr) & 0x0000fffffffff000ULL) | ((xid)<<ATE_TIDSHIFT) | (attr) 660 #define BRIDGE_INTERNAL_ATES 128 661 struct bridge_controller { 662 struct pci_controller pc; 663 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 664 struct resource mem; 665 struct resource io; 666 bridge_t *base; 667 nasid_t nasid; 668 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 669 unsigned int widget_id; 670 unsigned int irq_cpu; 671 dma64_addr_t baddr; 672 unsigned int pci_int[8]; 673 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 674 }; 675 #define BRIDGE_CONTROLLER(bus) ((struct bridge_controller *)((bus)->sysdata)) 676 #endif 677
