1 // Copyright 2011 the V8 project authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 5 #ifndef V8_ARM_CONSTANTS_ARM_H_ 6 #define V8_ARM_CONSTANTS_ARM_H_ 7 8 // ARM EABI is required. 9 #if defined(__arm__) && !defined(__ARM_EABI__) 10 #error ARM EABI support is required. 11 #endif 12 13 namespace v8 { 14 namespace internal { 15 16 // Constant pool marker. 17 // Use UDF, the permanently undefined instruction. 18 const int kConstantPoolMarkerMask = 0xfff000f0; 19 const int kConstantPoolMarker = 0xe7f000f0; 20 const int kConstantPoolLengthMaxMask = 0xffff; 21 inline int EncodeConstantPoolLength(int length) { 22 DCHECK((length & kConstantPoolLengthMaxMask) == length); 23 return ((length & 0xfff0) << 4) | (length & 0xf); 24 } 25 inline int DecodeConstantPoolLength(int instr) { 26 DCHECK((instr & kConstantPoolMarkerMask) == kConstantPoolMarker); 27 return ((instr >> 4) & 0xfff0) | (instr & 0xf); 28 } 29 30 // Used in code age prologue - ldr(pc, MemOperand(pc, -4)) 31 const int kCodeAgeJumpInstruction = 0xe51ff004; 32 33 // Number of registers in normal ARM mode. 34 const int kNumRegisters = 16; 35 36 // VFP support. 37 const int kNumVFPSingleRegisters = 32; 38 const int kNumVFPDoubleRegisters = 32; 39 const int kNumVFPRegisters = kNumVFPSingleRegisters + kNumVFPDoubleRegisters; 40 41 // PC is register 15. 42 const int kPCRegister = 15; 43 const int kNoRegister = -1; 44 45 // ----------------------------------------------------------------------------- 46 // Conditions. 47 48 // Defines constants and accessor classes to assemble, disassemble and 49 // simulate ARM instructions. 50 // 51 // Section references in the code refer to the "ARM Architecture Reference 52 // Manual" from July 2005 (available at http://www.arm.com/miscPDFs/14128.pdf) 53 // 54 // Constants for specific fields are defined in their respective named enums. 55 // General constants are in an anonymous enum in class Instr. 56 57 // Values for the condition field as defined in section A3.2 58 enum Condition { 59 kNoCondition = -1, 60 61 eq = 0 << 28, // Z set Equal. 62 ne = 1 << 28, // Z clear Not equal. 63 cs = 2 << 28, // C set Unsigned higher or same. 64 cc = 3 << 28, // C clear Unsigned lower. 65 mi = 4 << 28, // N set Negative. 66 pl = 5 << 28, // N clear Positive or zero. 67 vs = 6 << 28, // V set Overflow. 68 vc = 7 << 28, // V clear No overflow. 69 hi = 8 << 28, // C set, Z clear Unsigned higher. 70 ls = 9 << 28, // C clear or Z set Unsigned lower or same. 71 ge = 10 << 28, // N == V Greater or equal. 72 lt = 11 << 28, // N != V Less than. 73 gt = 12 << 28, // Z clear, N == V Greater than. 74 le = 13 << 28, // Z set or N != V Less then or equal 75 al = 14 << 28, // Always. 76 77 kSpecialCondition = 15 << 28, // Special condition (refer to section A3.2.1). 78 kNumberOfConditions = 16, 79 80 // Aliases. 81 hs = cs, // C set Unsigned higher or same. 82 lo = cc // C clear Unsigned lower. 83 }; 84 85 86 inline Condition NegateCondition(Condition cond) { 87 DCHECK(cond != al); 88 return static_cast<Condition>(cond ^ ne); 89 } 90 91 92 // Commute a condition such that {a cond b == b cond' a}. 93 inline Condition CommuteCondition(Condition cond) { 94 switch (cond) { 95 case lo: 96 return hi; 97 case hi: 98 return lo; 99 case hs: 100 return ls; 101 case ls: 102 return hs; 103 case lt: 104 return gt; 105 case gt: 106 return lt; 107 case ge: 108 return le; 109 case le: 110 return ge; 111 default: 112 return cond; 113 } 114 } 115 116 117 // ----------------------------------------------------------------------------- 118 // Instructions encoding. 119 120 // Instr is merely used by the Assembler to distinguish 32bit integers 121 // representing instructions from usual 32 bit values. 122 // Instruction objects are pointers to 32bit values, and provide methods to 123 // access the various ISA fields. 124 typedef int32_t Instr; 125 126 127 // Opcodes for Data-processing instructions (instructions with a type 0 and 1) 128 // as defined in section A3.4 129 enum Opcode { 130 AND = 0 << 21, // Logical AND. 131 EOR = 1 << 21, // Logical Exclusive OR. 132 SUB = 2 << 21, // Subtract. 133 RSB = 3 << 21, // Reverse Subtract. 134 ADD = 4 << 21, // Add. 135 ADC = 5 << 21, // Add with Carry. 136 SBC = 6 << 21, // Subtract with Carry. 137 RSC = 7 << 21, // Reverse Subtract with Carry. 138 TST = 8 << 21, // Test. 139 TEQ = 9 << 21, // Test Equivalence. 140 CMP = 10 << 21, // Compare. 141 CMN = 11 << 21, // Compare Negated. 142 ORR = 12 << 21, // Logical (inclusive) OR. 143 MOV = 13 << 21, // Move. 144 BIC = 14 << 21, // Bit Clear. 145 MVN = 15 << 21 // Move Not. 146 }; 147 148 149 // The bits for bit 7-4 for some type 0 miscellaneous instructions. 150 enum MiscInstructionsBits74 { 151 // With bits 22-21 01. 152 BX = 1 << 4, 153 BXJ = 2 << 4, 154 BLX = 3 << 4, 155 BKPT = 7 << 4, 156 157 // With bits 22-21 11. 158 CLZ = 1 << 4 159 }; 160 161 162 // Instruction encoding bits and masks. 163 enum { 164 H = 1 << 5, // Halfword (or byte). 165 S6 = 1 << 6, // Signed (or unsigned). 166 L = 1 << 20, // Load (or store). 167 S = 1 << 20, // Set condition code (or leave unchanged). 168 W = 1 << 21, // Writeback base register (or leave unchanged). 169 A = 1 << 21, // Accumulate in multiply instruction (or not). 170 B = 1 << 22, // Unsigned byte (or word). 171 N = 1 << 22, // Long (or short). 172 U = 1 << 23, // Positive (or negative) offset/index. 173 P = 1 << 24, // Offset/pre-indexed addressing (or post-indexed addressing). 174 I = 1 << 25, // Immediate shifter operand (or not). 175 176 B4 = 1 << 4, 177 B5 = 1 << 5, 178 B6 = 1 << 6, 179 B7 = 1 << 7, 180 B8 = 1 << 8, 181 B9 = 1 << 9, 182 B12 = 1 << 12, 183 B16 = 1 << 16, 184 B18 = 1 << 18, 185 B19 = 1 << 19, 186 B20 = 1 << 20, 187 B21 = 1 << 21, 188 B22 = 1 << 22, 189 B23 = 1 << 23, 190 B24 = 1 << 24, 191 B25 = 1 << 25, 192 B26 = 1 << 26, 193 B27 = 1 << 27, 194 B28 = 1 << 28, 195 196 // Instruction bit masks. 197 kCondMask = 15 << 28, 198 kALUMask = 0x6f << 21, 199 kRdMask = 15 << 12, // In str instruction. 200 kCoprocessorMask = 15 << 8, 201 kOpCodeMask = 15 << 21, // In data-processing instructions. 202 kImm24Mask = (1 << 24) - 1, 203 kImm16Mask = (1 << 16) - 1, 204 kImm8Mask = (1 << 8) - 1, 205 kOff12Mask = (1 << 12) - 1, 206 kOff8Mask = (1 << 8) - 1 207 }; 208 209 210 // ----------------------------------------------------------------------------- 211 // Addressing modes and instruction variants. 212 213 // Condition code updating mode. 214 enum SBit { 215 SetCC = 1 << 20, // Set condition code. 216 LeaveCC = 0 << 20 // Leave condition code unchanged. 217 }; 218 219 220 // Status register selection. 221 enum SRegister { 222 CPSR = 0 << 22, 223 SPSR = 1 << 22 224 }; 225 226 227 // Shifter types for Data-processing operands as defined in section A5.1.2. 228 enum ShiftOp { 229 LSL = 0 << 5, // Logical shift left. 230 LSR = 1 << 5, // Logical shift right. 231 ASR = 2 << 5, // Arithmetic shift right. 232 ROR = 3 << 5, // Rotate right. 233 234 // RRX is encoded as ROR with shift_imm == 0. 235 // Use a special code to make the distinction. The RRX ShiftOp is only used 236 // as an argument, and will never actually be encoded. The Assembler will 237 // detect it and emit the correct ROR shift operand with shift_imm == 0. 238 RRX = -1, 239 kNumberOfShifts = 4 240 }; 241 242 243 // Status register fields. 244 enum SRegisterField { 245 CPSR_c = CPSR | 1 << 16, 246 CPSR_x = CPSR | 1 << 17, 247 CPSR_s = CPSR | 1 << 18, 248 CPSR_f = CPSR | 1 << 19, 249 SPSR_c = SPSR | 1 << 16, 250 SPSR_x = SPSR | 1 << 17, 251 SPSR_s = SPSR | 1 << 18, 252 SPSR_f = SPSR | 1 << 19 253 }; 254 255 // Status register field mask (or'ed SRegisterField enum values). 256 typedef uint32_t SRegisterFieldMask; 257 258 259 // Memory operand addressing mode. 260 enum AddrMode { 261 // Bit encoding P U W. 262 Offset = (8|4|0) << 21, // Offset (without writeback to base). 263 PreIndex = (8|4|1) << 21, // Pre-indexed addressing with writeback. 264 PostIndex = (0|4|0) << 21, // Post-indexed addressing with writeback. 265 NegOffset = (8|0|0) << 21, // Negative offset (without writeback to base). 266 NegPreIndex = (8|0|1) << 21, // Negative pre-indexed with writeback. 267 NegPostIndex = (0|0|0) << 21 // Negative post-indexed with writeback. 268 }; 269 270 271 // Load/store multiple addressing mode. 272 enum BlockAddrMode { 273 // Bit encoding P U W . 274 da = (0|0|0) << 21, // Decrement after. 275 ia = (0|4|0) << 21, // Increment after. 276 db = (8|0|0) << 21, // Decrement before. 277 ib = (8|4|0) << 21, // Increment before. 278 da_w = (0|0|1) << 21, // Decrement after with writeback to base. 279 ia_w = (0|4|1) << 21, // Increment after with writeback to base. 280 db_w = (8|0|1) << 21, // Decrement before with writeback to base. 281 ib_w = (8|4|1) << 21, // Increment before with writeback to base. 282 283 // Alias modes for comparison when writeback does not matter. 284 da_x = (0|0|0) << 21, // Decrement after. 285 ia_x = (0|4|0) << 21, // Increment after. 286 db_x = (8|0|0) << 21, // Decrement before. 287 ib_x = (8|4|0) << 21, // Increment before. 288 289 kBlockAddrModeMask = (8|4|1) << 21 290 }; 291 292 293 // Coprocessor load/store operand size. 294 enum LFlag { 295 Long = 1 << 22, // Long load/store coprocessor. 296 Short = 0 << 22 // Short load/store coprocessor. 297 }; 298 299 300 // NEON data type 301 enum NeonDataType { 302 NeonS8 = 0x1, // U = 0, imm3 = 0b001 303 NeonS16 = 0x2, // U = 0, imm3 = 0b010 304 NeonS32 = 0x4, // U = 0, imm3 = 0b100 305 NeonU8 = 1 << 24 | 0x1, // U = 1, imm3 = 0b001 306 NeonU16 = 1 << 24 | 0x2, // U = 1, imm3 = 0b010 307 NeonU32 = 1 << 24 | 0x4, // U = 1, imm3 = 0b100 308 NeonDataTypeSizeMask = 0x7, 309 NeonDataTypeUMask = 1 << 24 310 }; 311 312 enum NeonListType { 313 nlt_1 = 0x7, 314 nlt_2 = 0xA, 315 nlt_3 = 0x6, 316 nlt_4 = 0x2 317 }; 318 319 enum NeonSize { 320 Neon8 = 0x0, 321 Neon16 = 0x1, 322 Neon32 = 0x2, 323 Neon64 = 0x3 324 }; 325 326 // ----------------------------------------------------------------------------- 327 // Supervisor Call (svc) specific support. 328 329 // Special Software Interrupt codes when used in the presence of the ARM 330 // simulator. 331 // svc (formerly swi) provides a 24bit immediate value. Use bits 22:0 for 332 // standard SoftwareInterrupCode. Bit 23 is reserved for the stop feature. 333 enum SoftwareInterruptCodes { 334 // transition to C code 335 kCallRtRedirected= 0x10, 336 // break point 337 kBreakpoint= 0x20, 338 // stop 339 kStopCode = 1 << 23 340 }; 341 const uint32_t kStopCodeMask = kStopCode - 1; 342 const uint32_t kMaxStopCode = kStopCode - 1; 343 const int32_t kDefaultStopCode = -1; 344 345 346 // Type of VFP register. Determines register encoding. 347 enum VFPRegPrecision { 348 kSinglePrecision = 0, 349 kDoublePrecision = 1 350 }; 351 352 353 // VFP FPSCR constants. 354 enum VFPConversionMode { 355 kFPSCRRounding = 0, 356 kDefaultRoundToZero = 1 357 }; 358 359 // This mask does not include the "inexact" or "input denormal" cumulative 360 // exceptions flags, because we usually don't want to check for it. 361 const uint32_t kVFPExceptionMask = 0xf; 362 const uint32_t kVFPInvalidOpExceptionBit = 1 << 0; 363 const uint32_t kVFPOverflowExceptionBit = 1 << 2; 364 const uint32_t kVFPUnderflowExceptionBit = 1 << 3; 365 const uint32_t kVFPInexactExceptionBit = 1 << 4; 366 const uint32_t kVFPFlushToZeroMask = 1 << 24; 367 const uint32_t kVFPDefaultNaNModeControlBit = 1 << 25; 368 369 const uint32_t kVFPNConditionFlagBit = 1 << 31; 370 const uint32_t kVFPZConditionFlagBit = 1 << 30; 371 const uint32_t kVFPCConditionFlagBit = 1 << 29; 372 const uint32_t kVFPVConditionFlagBit = 1 << 28; 373 374 375 // VFP rounding modes. See ARM DDI 0406B Page A2-29. 376 enum VFPRoundingMode { 377 RN = 0 << 22, // Round to Nearest. 378 RP = 1 << 22, // Round towards Plus Infinity. 379 RM = 2 << 22, // Round towards Minus Infinity. 380 RZ = 3 << 22, // Round towards zero. 381 382 // Aliases. 383 kRoundToNearest = RN, 384 kRoundToPlusInf = RP, 385 kRoundToMinusInf = RM, 386 kRoundToZero = RZ 387 }; 388 389 const uint32_t kVFPRoundingModeMask = 3 << 22; 390 391 enum CheckForInexactConversion { 392 kCheckForInexactConversion, 393 kDontCheckForInexactConversion 394 }; 395 396 // ----------------------------------------------------------------------------- 397 // Hints. 398 399 // Branch hints are not used on the ARM. They are defined so that they can 400 // appear in shared function signatures, but will be ignored in ARM 401 // implementations. 402 enum Hint { no_hint }; 403 404 // Hints are not used on the arm. Negating is trivial. 405 inline Hint NegateHint(Hint ignored) { return no_hint; } 406 407 408 // ----------------------------------------------------------------------------- 409 // Instruction abstraction. 410 411 // The class Instruction enables access to individual fields defined in the ARM 412 // architecture instruction set encoding as described in figure A3-1. 413 // Note that the Assembler uses typedef int32_t Instr. 414 // 415 // Example: Test whether the instruction at ptr does set the condition code 416 // bits. 417 // 418 // bool InstructionSetsConditionCodes(byte* ptr) { 419 // Instruction* instr = Instruction::At(ptr); 420 // int type = instr->TypeValue(); 421 // return ((type == 0) || (type == 1)) && instr->HasS(); 422 // } 423 // 424 class Instruction { 425 public: 426 enum { 427 kInstrSize = 4, 428 kInstrSizeLog2 = 2, 429 kPCReadOffset = 8 430 }; 431 432 // Helper macro to define static accessors. 433 // We use the cast to char* trick to bypass the strict anti-aliasing rules. 434 #define DECLARE_STATIC_TYPED_ACCESSOR(return_type, Name) \ 435 static inline return_type Name(Instr instr) { \ 436 char* temp = reinterpret_cast<char*>(&instr); \ 437 return reinterpret_cast<Instruction*>(temp)->Name(); \ 438 } 439 440 #define DECLARE_STATIC_ACCESSOR(Name) DECLARE_STATIC_TYPED_ACCESSOR(int, Name) 441 442 // Get the raw instruction bits. 443 inline Instr InstructionBits() const { 444 return *reinterpret_cast<const Instr*>(this); 445 } 446 447 // Set the raw instruction bits to value. 448 inline void SetInstructionBits(Instr value) { 449 *reinterpret_cast<Instr*>(this) = value; 450 } 451 452 // Read one particular bit out of the instruction bits. 453 inline int Bit(int nr) const { 454 return (InstructionBits() >> nr) & 1; 455 } 456 457 // Read a bit field's value out of the instruction bits. 458 inline int Bits(int hi, int lo) const { 459 return (InstructionBits() >> lo) & ((2 << (hi - lo)) - 1); 460 } 461 462 // Read a bit field out of the instruction bits. 463 inline int BitField(int hi, int lo) const { 464 return InstructionBits() & (((2 << (hi - lo)) - 1) << lo); 465 } 466 467 // Static support. 468 469 // Read one particular bit out of the instruction bits. 470 static inline int Bit(Instr instr, int nr) { 471 return (instr >> nr) & 1; 472 } 473 474 // Read the value of a bit field out of the instruction bits. 475 static inline int Bits(Instr instr, int hi, int lo) { 476 return (instr >> lo) & ((2 << (hi - lo)) - 1); 477 } 478 479 480 // Read a bit field out of the instruction bits. 481 static inline int BitField(Instr instr, int hi, int lo) { 482 return instr & (((2 << (hi - lo)) - 1) << lo); 483 } 484 485 486 // Accessors for the different named fields used in the ARM encoding. 487 // The naming of these accessor corresponds to figure A3-1. 488 // 489 // Two kind of accessors are declared: 490 // - <Name>Field() will return the raw field, i.e. the field's bits at their 491 // original place in the instruction encoding. 492 // e.g. if instr is the 'addgt r0, r1, r2' instruction, encoded as 493 // 0xC0810002 ConditionField(instr) will return 0xC0000000. 494 // - <Name>Value() will return the field value, shifted back to bit 0. 495 // e.g. if instr is the 'addgt r0, r1, r2' instruction, encoded as 496 // 0xC0810002 ConditionField(instr) will return 0xC. 497 498 499 // Generally applicable fields 500 inline Condition ConditionValue() const { 501 return static_cast<Condition>(Bits(31, 28)); 502 } 503 inline Condition ConditionField() const { 504 return static_cast<Condition>(BitField(31, 28)); 505 } 506 DECLARE_STATIC_TYPED_ACCESSOR(Condition, ConditionValue); 507 DECLARE_STATIC_TYPED_ACCESSOR(Condition, ConditionField); 508 509 inline int TypeValue() const { return Bits(27, 25); } 510 inline int SpecialValue() const { return Bits(27, 23); } 511 512 inline int RnValue() const { return Bits(19, 16); } 513 DECLARE_STATIC_ACCESSOR(RnValue); 514 inline int RdValue() const { return Bits(15, 12); } 515 DECLARE_STATIC_ACCESSOR(RdValue); 516 517 inline int CoprocessorValue() const { return Bits(11, 8); } 518 // Support for VFP. 519 // Vn(19-16) | Vd(15-12) | Vm(3-0) 520 inline int VnValue() const { return Bits(19, 16); } 521 inline int VmValue() const { return Bits(3, 0); } 522 inline int VdValue() const { return Bits(15, 12); } 523 inline int NValue() const { return Bit(7); } 524 inline int MValue() const { return Bit(5); } 525 inline int DValue() const { return Bit(22); } 526 inline int RtValue() const { return Bits(15, 12); } 527 inline int PValue() const { return Bit(24); } 528 inline int UValue() const { return Bit(23); } 529 inline int Opc1Value() const { return (Bit(23) << 2) | Bits(21, 20); } 530 inline int Opc2Value() const { return Bits(19, 16); } 531 inline int Opc3Value() const { return Bits(7, 6); } 532 inline int SzValue() const { return Bit(8); } 533 inline int VLValue() const { return Bit(20); } 534 inline int VCValue() const { return Bit(8); } 535 inline int VAValue() const { return Bits(23, 21); } 536 inline int VBValue() const { return Bits(6, 5); } 537 inline int VFPNRegValue(VFPRegPrecision pre) { 538 return VFPGlueRegValue(pre, 16, 7); 539 } 540 inline int VFPMRegValue(VFPRegPrecision pre) { 541 return VFPGlueRegValue(pre, 0, 5); 542 } 543 inline int VFPDRegValue(VFPRegPrecision pre) { 544 return VFPGlueRegValue(pre, 12, 22); 545 } 546 547 // Fields used in Data processing instructions 548 inline int OpcodeValue() const { 549 return static_cast<Opcode>(Bits(24, 21)); 550 } 551 inline Opcode OpcodeField() const { 552 return static_cast<Opcode>(BitField(24, 21)); 553 } 554 inline int SValue() const { return Bit(20); } 555 // with register 556 inline int RmValue() const { return Bits(3, 0); } 557 DECLARE_STATIC_ACCESSOR(RmValue); 558 inline int ShiftValue() const { return static_cast<ShiftOp>(Bits(6, 5)); } 559 inline ShiftOp ShiftField() const { 560 return static_cast<ShiftOp>(BitField(6, 5)); 561 } 562 inline int RegShiftValue() const { return Bit(4); } 563 inline int RsValue() const { return Bits(11, 8); } 564 inline int ShiftAmountValue() const { return Bits(11, 7); } 565 // with immediate 566 inline int RotateValue() const { return Bits(11, 8); } 567 DECLARE_STATIC_ACCESSOR(RotateValue); 568 inline int Immed8Value() const { return Bits(7, 0); } 569 DECLARE_STATIC_ACCESSOR(Immed8Value); 570 inline int Immed4Value() const { return Bits(19, 16); } 571 inline int ImmedMovwMovtValue() const { 572 return Immed4Value() << 12 | Offset12Value(); } 573 DECLARE_STATIC_ACCESSOR(ImmedMovwMovtValue); 574 575 // Fields used in Load/Store instructions 576 inline int PUValue() const { return Bits(24, 23); } 577 inline int PUField() const { return BitField(24, 23); } 578 inline int BValue() const { return Bit(22); } 579 inline int WValue() const { return Bit(21); } 580 inline int LValue() const { return Bit(20); } 581 // with register uses same fields as Data processing instructions above 582 // with immediate 583 inline int Offset12Value() const { return Bits(11, 0); } 584 // multiple 585 inline int RlistValue() const { return Bits(15, 0); } 586 // extra loads and stores 587 inline int SignValue() const { return Bit(6); } 588 inline int HValue() const { return Bit(5); } 589 inline int ImmedHValue() const { return Bits(11, 8); } 590 inline int ImmedLValue() const { return Bits(3, 0); } 591 592 // Fields used in Branch instructions 593 inline int LinkValue() const { return Bit(24); } 594 inline int SImmed24Value() const { return ((InstructionBits() << 8) >> 8); } 595 596 // Fields used in Software interrupt instructions 597 inline SoftwareInterruptCodes SvcValue() const { 598 return static_cast<SoftwareInterruptCodes>(Bits(23, 0)); 599 } 600 601 // Test for special encodings of type 0 instructions (extra loads and stores, 602 // as well as multiplications). 603 inline bool IsSpecialType0() const { return (Bit(7) == 1) && (Bit(4) == 1); } 604 605 // Test for miscellaneous instructions encodings of type 0 instructions. 606 inline bool IsMiscType0() const { return (Bit(24) == 1) 607 && (Bit(23) == 0) 608 && (Bit(20) == 0) 609 && ((Bit(7) == 0)); } 610 611 // Test for a nop instruction, which falls under type 1. 612 inline bool IsNopType1() const { return Bits(24, 0) == 0x0120F000; } 613 614 // Test for a stop instruction. 615 inline bool IsStop() const { 616 return (TypeValue() == 7) && (Bit(24) == 1) && (SvcValue() >= kStopCode); 617 } 618 619 // Special accessors that test for existence of a value. 620 inline bool HasS() const { return SValue() == 1; } 621 inline bool HasB() const { return BValue() == 1; } 622 inline bool HasW() const { return WValue() == 1; } 623 inline bool HasL() const { return LValue() == 1; } 624 inline bool HasU() const { return UValue() == 1; } 625 inline bool HasSign() const { return SignValue() == 1; } 626 inline bool HasH() const { return HValue() == 1; } 627 inline bool HasLink() const { return LinkValue() == 1; } 628 629 // Decoding the double immediate in the vmov instruction. 630 double DoubleImmedVmov() const; 631 632 // Instructions are read of out a code stream. The only way to get a 633 // reference to an instruction is to convert a pointer. There is no way 634 // to allocate or create instances of class Instruction. 635 // Use the At(pc) function to create references to Instruction. 636 static Instruction* At(byte* pc) { 637 return reinterpret_cast<Instruction*>(pc); 638 } 639 640 641 private: 642 // Join split register codes, depending on single or double precision. 643 // four_bit is the position of the least-significant bit of the four 644 // bit specifier. one_bit is the position of the additional single bit 645 // specifier. 646 inline int VFPGlueRegValue(VFPRegPrecision pre, int four_bit, int one_bit) { 647 if (pre == kSinglePrecision) { 648 return (Bits(four_bit + 3, four_bit) << 1) | Bit(one_bit); 649 } 650 return (Bit(one_bit) << 4) | Bits(four_bit + 3, four_bit); 651 } 652 653 // We need to prevent the creation of instances of class Instruction. 654 DISALLOW_IMPLICIT_CONSTRUCTORS(Instruction); 655 }; 656 657 658 // Helper functions for converting between register numbers and names. 659 class Registers { 660 public: 661 // Return the name of the register. 662 static const char* Name(int reg); 663 664 // Lookup the register number for the name provided. 665 static int Number(const char* name); 666 667 struct RegisterAlias { 668 int reg; 669 const char* name; 670 }; 671 672 private: 673 static const char* names_[kNumRegisters]; 674 static const RegisterAlias aliases_[]; 675 }; 676 677 // Helper functions for converting between VFP register numbers and names. 678 class VFPRegisters { 679 public: 680 // Return the name of the register. 681 static const char* Name(int reg, bool is_double); 682 683 // Lookup the register number for the name provided. 684 // Set flag pointed by is_double to true if register 685 // is double-precision. 686 static int Number(const char* name, bool* is_double); 687 688 private: 689 static const char* names_[kNumVFPRegisters]; 690 }; 691 692 693 } } // namespace v8::internal 694 695 #endif // V8_ARM_CONSTANTS_ARM_H_ 696
