| /external/llvm/lib/CodeGen/ |
| CallingConvLower.cpp | 122 unsigned NumOps = Outs.size();
123 for (unsigned i = 0; i != NumOps; ++i) {
141 unsigned NumOps = ArgVTs.size();
142 for (unsigned i = 0; i != NumOps; ++i) {
|
| MachineRegisterInfo.cpp | 135 unsigned NumOps = MI->getNumOperands();
136 if (!(MO >= MO0 && MO < MO0+NumOps)) {
230 /// Move NumOps operands from Src to Dst, updating use-def lists as needed.
239 unsigned NumOps) {
240 assert(Src != Dst && NumOps && "Noop moveOperands");
244 if (Dst >= Src && Dst < Src + NumOps) {
246 Dst += NumOps - 1;
247 Src += NumOps - 1;
276 } while (--NumOps);
|
| MachineInstr.cpp | 596 if (unsigned NumOps = MCID->getNumOperands() +
598 CapOperands = OperandCapacity::get(NumOps);
661 /// Move NumOps MachineOperands from Src to Dst, with support for overlapping
664 unsigned NumOps, MachineRegisterInfo *MRI) {
666 return MRI->moveOperands(Dst, Src, NumOps);
669 std::memmove(Dst, Src, NumOps * sizeof(MachineOperand));
[all...] |
| MachineVerifier.cpp | 745 unsigned NumOps;
746 for (unsigned e = MI->getNumOperands(); OpNo < e; OpNo += NumOps) {
751 NumOps = 1 + InlineAsm::getNumOperandRegisters(MO.getImm());
[all...] |
| TwoAddressInstructionPass.cpp | 478 for (unsigned i = 0, NumOps = MI.getNumOperands(); i != NumOps; ++i) {
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGSDNodes.cpp | 204 unsigned NumOps = Node->getNumOperands();
205 if (Node->getOperand(NumOps-1).getValueType() == MVT::Other)
206 Chain = Node->getOperand(NumOps-1).getNode();
[all...] |
| LegalizeTypes.cpp | 425 for (unsigned i = 0, NumOps = I->getNumOperands(); i < NumOps; ++i)
[all...] |
| ScheduleDAGFast.cpp | 494 unsigned NumOps = Node->getNumOperands();
495 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
496 --NumOps; // Ignore the glue operand.
498 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
682 unsigned NumOps = N->getNumOperands();
683 if (unsigned NumLeft = NumOps) {
689 if (NumLeft == NumOps && Op.getValueType() == MVT::Glue) {
|
| ScheduleDAGRRList.cpp | [all...] |
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86BaseInfo.h | 632 unsigned NumOps = Desc.getNumOperands();
634 if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) == 0)
636 else if (NumOps > 3 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 &&
641 else if (NumOps > 3 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 &&
642 Desc.getOperandConstraint(NumOps - 1, MCOI::TIED_TO) == 1)
646 else if (NumOps > 2 && Desc.getOperandConstraint(NumOps - 2, MCOI::TIED_TO) == 0)
|
| X86MCCodeEmitter.cpp | 711 unsigned NumOps = Desc.getNumOperands();
861 unsigned RcOperand = NumOps-1;
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86CallFrameOptimization.cpp | 415 unsigned NumOps = DefMov->getDesc().getNumOperands();
416 for (unsigned i = NumOps - X86::AddrNumOperands; i != NumOps; ++i)
|
| X86FloatingPoint.cpp | [all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenInstruction.cpp | 72 unsigned NumOps = 1;
94 NumOps = NumArgs;
120 MIOperandNo, NumOps, MIOpInfo));
121 MIOperandNo += NumOps;
|
| DAGISelMatcherEmitter.cpp | 664 unsigned NumOps = P.getNumOperands();
667 ++NumOps; // Get the chained node too.
670 OS << " Result.resize(NextRes+" << NumOps << ");\n";
685 for (unsigned i = 0; i != NumOps; ++i)
|
| AsmWriterEmitter.cpp | 383 unsigned NumOps = NumInstOpsHandled[InstIdxs[i]];
384 assert(NumOps <= Inst->Operands.size() &&
387 Inst->Operands.begin()+NumOps);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb2SizeReduction.cpp | 700 unsigned NumOps = MCID.getNumOperands();
701 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR);
702 if (HasCC && MI->getOperand(NumOps-1).isDead())
726 unsigned NumOps = MCID.getNumOperands();
728 if (i < NumOps && MCID.OpInfo[i].isOptionalDef())
796 unsigned NumOps = MCID.getNumOperands();
797 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR);
798 if (HasCC && MI->getOperand(NumOps-1).isDead())
822 unsigned NumOps = MCID.getNumOperands();
824 if (i < NumOps && MCID.OpInfo[i].isOptionalDef()
[all...] |
| ARMConstantIslandPass.cpp | [all...] |
| ARMISelDAGToDAG.cpp | [all...] |
| ARMBaseInstrInfo.cpp | 158 unsigned NumOps = MCID.getNumOperands();
162 const MachineOperand &Offset = MI->getOperand(NumOps-3);
166 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
167 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
654 unsigned NumOps = MCID.getNumOperands();
656 MI->getOperand(NumOps - (MI->isPredicable() ? 3 : 2));
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| Scalarizer.cpp | 570 unsigned NumOps = PHI.getNumOperands();
572 Res[I] = Builder.CreatePHI(VT->getElementType(), NumOps,
575 for (unsigned I = 0; I < NumOps; ++I) {
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrInfo.cpp | 663 unsigned NumOps = OldMI->getNumOperands();
664 for (unsigned I = 1; I < NumOps; ++I) {
682 unsigned NumOps = MI->getNumOperands();
712 for (unsigned I = 2; I < NumOps; ++I)
846 unsigned NumOps = MI->getNumExplicitOperands();
847 if (OpNum == NumOps - 1) {
[all...] |
| /external/llvm/lib/IR/ |
| Instructions.cpp | 144 unsigned NumOps = e + e / 2;
145 if (NumOps < 2) NumOps = 2; // 2 op PHI nodes are VERY common.
150 ReservedSpace = NumOps;
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 709 unsigned NumOps = Node->getNumOperands();
710 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
711 --NumOps; // Ignore the flag operand.
713 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
[all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | 579 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
581 for (unsigned i = 0; i < NumOps; ++i, ++I) {
644 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
646 for (unsigned i = 0; i < NumOps; ++i, ++I) {
682 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
683 for (unsigned i = 0; i < NumOps; ++i, ++I) {
[all...] |
