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      1 //===- CodeGenRegisters.h - Register and RegisterClass Info -----*- C++ -*-===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file defines structures to encapsulate information gleaned from the
     11 // target register and register class definitions.
     12 //
     13 //===----------------------------------------------------------------------===//
     14 
     15 #ifndef LLVM_UTILS_TABLEGEN_CODEGENREGISTERS_H
     16 #define LLVM_UTILS_TABLEGEN_CODEGENREGISTERS_H
     17 
     18 #include "llvm/ADT/ArrayRef.h"
     19 #include "llvm/ADT/BitVector.h"
     20 #include "llvm/ADT/DenseMap.h"
     21 #include "llvm/ADT/STLExtras.h"
     22 #include "llvm/ADT/SetVector.h"
     23 #include "llvm/ADT/SparseBitVector.h"
     24 #include "llvm/CodeGen/MachineValueType.h"
     25 #include "llvm/Support/ErrorHandling.h"
     26 #include "llvm/TableGen/Record.h"
     27 #include "llvm/TableGen/SetTheory.h"
     28 #include <cstdlib>
     29 #include <list>
     30 #include <map>
     31 #include <set>
     32 #include <string>
     33 #include <vector>
     34 #include <deque>
     35 
     36 namespace llvm {
     37   class CodeGenRegBank;
     38 
     39   /// Used to encode a step in a register lane mask transformation.
     40   /// Mask the bits specified in Mask, then rotate them Rol bits to the left
     41   /// assuming a wraparound at 32bits.
     42   struct MaskRolPair {
     43     unsigned Mask;
     44     uint8_t RotateLeft;
     45     bool operator==(const MaskRolPair Other) const {
     46       return Mask == Other.Mask && RotateLeft == Other.RotateLeft;
     47     }
     48     bool operator!=(const MaskRolPair Other) const {
     49       return Mask != Other.Mask || RotateLeft != Other.RotateLeft;
     50     }
     51   };
     52 
     53   /// CodeGenSubRegIndex - Represents a sub-register index.
     54   class CodeGenSubRegIndex {
     55     Record *const TheDef;
     56     std::string Name;
     57     std::string Namespace;
     58 
     59   public:
     60     uint16_t Size;
     61     uint16_t Offset;
     62     const unsigned EnumValue;
     63     mutable unsigned LaneMask;
     64     mutable SmallVector<MaskRolPair,1> CompositionLaneMaskTransform;
     65 
     66     // Are all super-registers containing this SubRegIndex covered by their
     67     // sub-registers?
     68     bool AllSuperRegsCovered;
     69 
     70     CodeGenSubRegIndex(Record *R, unsigned Enum);
     71     CodeGenSubRegIndex(StringRef N, StringRef Nspace, unsigned Enum);
     72 
     73     const std::string &getName() const { return Name; }
     74     const std::string &getNamespace() const { return Namespace; }
     75     std::string getQualifiedName() const;
     76 
     77     // Map of composite subreg indices.
     78     typedef std::map<CodeGenSubRegIndex *, CodeGenSubRegIndex *,
     79                      deref<llvm::less>> CompMap;
     80 
     81     // Returns the subreg index that results from composing this with Idx.
     82     // Returns NULL if this and Idx don't compose.
     83     CodeGenSubRegIndex *compose(CodeGenSubRegIndex *Idx) const {
     84       CompMap::const_iterator I = Composed.find(Idx);
     85       return I == Composed.end() ? nullptr : I->second;
     86     }
     87 
     88     // Add a composite subreg index: this+A = B.
     89     // Return a conflicting composite, or NULL
     90     CodeGenSubRegIndex *addComposite(CodeGenSubRegIndex *A,
     91                                      CodeGenSubRegIndex *B) {
     92       assert(A && B);
     93       std::pair<CompMap::iterator, bool> Ins =
     94         Composed.insert(std::make_pair(A, B));
     95       // Synthetic subreg indices that aren't contiguous (for instance ARM
     96       // register tuples) don't have a bit range, so it's OK to let
     97       // B->Offset == -1. For the other cases, accumulate the offset and set
     98       // the size here. Only do so if there is no offset yet though.
     99       if ((Offset != (uint16_t)-1 && A->Offset != (uint16_t)-1) &&
    100           (B->Offset == (uint16_t)-1)) {
    101         B->Offset = Offset + A->Offset;
    102         B->Size = A->Size;
    103       }
    104       return (Ins.second || Ins.first->second == B) ? nullptr
    105                                                     : Ins.first->second;
    106     }
    107 
    108     // Update the composite maps of components specified in 'ComposedOf'.
    109     void updateComponents(CodeGenRegBank&);
    110 
    111     // Return the map of composites.
    112     const CompMap &getComposites() const { return Composed; }
    113 
    114     // Compute LaneMask from Composed. Return LaneMask.
    115     unsigned computeLaneMask() const;
    116 
    117   private:
    118     CompMap Composed;
    119   };
    120 
    121   inline bool operator<(const CodeGenSubRegIndex &A,
    122                         const CodeGenSubRegIndex &B) {
    123     return A.EnumValue < B.EnumValue;
    124   }
    125 
    126   /// CodeGenRegister - Represents a register definition.
    127   struct CodeGenRegister {
    128     Record *TheDef;
    129     unsigned EnumValue;
    130     unsigned CostPerUse;
    131     bool CoveredBySubRegs;
    132     bool HasDisjunctSubRegs;
    133 
    134     // Map SubRegIndex -> Register.
    135     typedef std::map<CodeGenSubRegIndex *, CodeGenRegister *, deref<llvm::less>>
    136         SubRegMap;
    137 
    138     CodeGenRegister(Record *R, unsigned Enum);
    139 
    140     const std::string &getName() const;
    141 
    142     // Extract more information from TheDef. This is used to build an object
    143     // graph after all CodeGenRegister objects have been created.
    144     void buildObjectGraph(CodeGenRegBank&);
    145 
    146     // Lazily compute a map of all sub-registers.
    147     // This includes unique entries for all sub-sub-registers.
    148     const SubRegMap &computeSubRegs(CodeGenRegBank&);
    149 
    150     // Compute extra sub-registers by combining the existing sub-registers.
    151     void computeSecondarySubRegs(CodeGenRegBank&);
    152 
    153     // Add this as a super-register to all sub-registers after the sub-register
    154     // graph has been built.
    155     void computeSuperRegs(CodeGenRegBank&);
    156 
    157     const SubRegMap &getSubRegs() const {
    158       assert(SubRegsComplete && "Must precompute sub-registers");
    159       return SubRegs;
    160     }
    161 
    162     // Add sub-registers to OSet following a pre-order defined by the .td file.
    163     void addSubRegsPreOrder(SetVector<const CodeGenRegister*> &OSet,
    164                             CodeGenRegBank&) const;
    165 
    166     // Return the sub-register index naming Reg as a sub-register of this
    167     // register. Returns NULL if Reg is not a sub-register.
    168     CodeGenSubRegIndex *getSubRegIndex(const CodeGenRegister *Reg) const {
    169       return SubReg2Idx.lookup(Reg);
    170     }
    171 
    172     typedef std::vector<const CodeGenRegister*> SuperRegList;
    173 
    174     // Get the list of super-registers in topological order, small to large.
    175     // This is valid after computeSubRegs visits all registers during RegBank
    176     // construction.
    177     const SuperRegList &getSuperRegs() const {
    178       assert(SubRegsComplete && "Must precompute sub-registers");
    179       return SuperRegs;
    180     }
    181 
    182     // Get the list of ad hoc aliases. The graph is symmetric, so the list
    183     // contains all registers in 'Aliases', and all registers that mention this
    184     // register in 'Aliases'.
    185     ArrayRef<CodeGenRegister*> getExplicitAliases() const {
    186       return ExplicitAliases;
    187     }
    188 
    189     // Get the topological signature of this register. This is a small integer
    190     // less than RegBank.getNumTopoSigs(). Registers with the same TopoSig have
    191     // identical sub-register structure. That is, they support the same set of
    192     // sub-register indices mapping to the same kind of sub-registers
    193     // (TopoSig-wise).
    194     unsigned getTopoSig() const {
    195       assert(SuperRegsComplete && "TopoSigs haven't been computed yet.");
    196       return TopoSig;
    197     }
    198 
    199     // List of register units in ascending order.
    200     typedef SparseBitVector<> RegUnitList;
    201     typedef SmallVector<unsigned, 16> RegUnitLaneMaskList;
    202 
    203     // How many entries in RegUnitList are native?
    204     RegUnitList NativeRegUnits;
    205 
    206     // Get the list of register units.
    207     // This is only valid after computeSubRegs() completes.
    208     const RegUnitList &getRegUnits() const { return RegUnits; }
    209 
    210     ArrayRef<unsigned> getRegUnitLaneMasks() const {
    211       return makeArrayRef(RegUnitLaneMasks).slice(0, NativeRegUnits.count());
    212     }
    213 
    214     // Get the native register units. This is a prefix of getRegUnits().
    215     RegUnitList getNativeRegUnits() const {
    216       return NativeRegUnits;
    217     }
    218 
    219     void setRegUnitLaneMasks(const RegUnitLaneMaskList &LaneMasks) {
    220       RegUnitLaneMasks = LaneMasks;
    221     }
    222 
    223     // Inherit register units from subregisters.
    224     // Return true if the RegUnits changed.
    225     bool inheritRegUnits(CodeGenRegBank &RegBank);
    226 
    227     // Adopt a register unit for pressure tracking.
    228     // A unit is adopted iff its unit number is >= NativeRegUnits.count().
    229     void adoptRegUnit(unsigned RUID) { RegUnits.set(RUID); }
    230 
    231     // Get the sum of this register's register unit weights.
    232     unsigned getWeight(const CodeGenRegBank &RegBank) const;
    233 
    234     // Canonically ordered set.
    235     typedef std::vector<const CodeGenRegister*> Vec;
    236 
    237   private:
    238     bool SubRegsComplete;
    239     bool SuperRegsComplete;
    240     unsigned TopoSig;
    241 
    242     // The sub-registers explicit in the .td file form a tree.
    243     SmallVector<CodeGenSubRegIndex*, 8> ExplicitSubRegIndices;
    244     SmallVector<CodeGenRegister*, 8> ExplicitSubRegs;
    245 
    246     // Explicit ad hoc aliases, symmetrized to form an undirected graph.
    247     SmallVector<CodeGenRegister*, 8> ExplicitAliases;
    248 
    249     // Super-registers where this is the first explicit sub-register.
    250     SuperRegList LeadingSuperRegs;
    251 
    252     SubRegMap SubRegs;
    253     SuperRegList SuperRegs;
    254     DenseMap<const CodeGenRegister*, CodeGenSubRegIndex*> SubReg2Idx;
    255     RegUnitList RegUnits;
    256     RegUnitLaneMaskList RegUnitLaneMasks;
    257   };
    258 
    259   inline bool operator<(const CodeGenRegister &A, const CodeGenRegister &B) {
    260     return A.EnumValue < B.EnumValue;
    261   }
    262 
    263   inline bool operator==(const CodeGenRegister &A, const CodeGenRegister &B) {
    264     return A.EnumValue == B.EnumValue;
    265   }
    266 
    267   class CodeGenRegisterClass {
    268     CodeGenRegister::Vec Members;
    269     // Allocation orders. Order[0] always contains all registers in Members.
    270     std::vector<SmallVector<Record*, 16> > Orders;
    271     // Bit mask of sub-classes including this, indexed by their EnumValue.
    272     BitVector SubClasses;
    273     // List of super-classes, topologocally ordered to have the larger classes
    274     // first.  This is the same as sorting by EnumValue.
    275     SmallVector<CodeGenRegisterClass*, 4> SuperClasses;
    276     Record *TheDef;
    277     std::string Name;
    278 
    279     // For a synthesized class, inherit missing properties from the nearest
    280     // super-class.
    281     void inheritProperties(CodeGenRegBank&);
    282 
    283     // Map SubRegIndex -> sub-class.  This is the largest sub-class where all
    284     // registers have a SubRegIndex sub-register.
    285     DenseMap<const CodeGenSubRegIndex *, CodeGenRegisterClass *>
    286         SubClassWithSubReg;
    287 
    288     // Map SubRegIndex -> set of super-reg classes.  This is all register
    289     // classes SuperRC such that:
    290     //
    291     //   R:SubRegIndex in this RC for all R in SuperRC.
    292     //
    293     DenseMap<const CodeGenSubRegIndex *, SmallPtrSet<CodeGenRegisterClass *, 8>>
    294         SuperRegClasses;
    295 
    296     // Bit vector of TopoSigs for the registers in this class. This will be
    297     // very sparse on regular architectures.
    298     BitVector TopoSigs;
    299 
    300   public:
    301     unsigned EnumValue;
    302     std::string Namespace;
    303     SmallVector<MVT::SimpleValueType, 4> VTs;
    304     unsigned SpillSize;
    305     unsigned SpillAlignment;
    306     int CopyCost;
    307     bool Allocatable;
    308     std::string AltOrderSelect;
    309     uint8_t AllocationPriority;
    310     /// Contains the combination of the lane masks of all subregisters.
    311     unsigned LaneMask;
    312     /// True if there are at least 2 subregisters which do not interfere.
    313     bool HasDisjunctSubRegs;
    314 
    315     // Return the Record that defined this class, or NULL if the class was
    316     // created by TableGen.
    317     Record *getDef() const { return TheDef; }
    318 
    319     const std::string &getName() const { return Name; }
    320     std::string getQualifiedName() const;
    321     ArrayRef<MVT::SimpleValueType> getValueTypes() const {return VTs;}
    322     unsigned getNumValueTypes() const { return VTs.size(); }
    323 
    324     MVT::SimpleValueType getValueTypeNum(unsigned VTNum) const {
    325       if (VTNum < VTs.size())
    326         return VTs[VTNum];
    327       llvm_unreachable("VTNum greater than number of ValueTypes in RegClass!");
    328     }
    329 
    330     // Return true if this this class contains the register.
    331     bool contains(const CodeGenRegister*) const;
    332 
    333     // Returns true if RC is a subclass.
    334     // RC is a sub-class of this class if it is a valid replacement for any
    335     // instruction operand where a register of this classis required. It must
    336     // satisfy these conditions:
    337     //
    338     // 1. All RC registers are also in this.
    339     // 2. The RC spill size must not be smaller than our spill size.
    340     // 3. RC spill alignment must be compatible with ours.
    341     //
    342     bool hasSubClass(const CodeGenRegisterClass *RC) const {
    343       return SubClasses.test(RC->EnumValue);
    344     }
    345 
    346     // getSubClassWithSubReg - Returns the largest sub-class where all
    347     // registers have a SubIdx sub-register.
    348     CodeGenRegisterClass *
    349     getSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx) const {
    350       return SubClassWithSubReg.lookup(SubIdx);
    351     }
    352 
    353     void setSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx,
    354                                CodeGenRegisterClass *SubRC) {
    355       SubClassWithSubReg[SubIdx] = SubRC;
    356     }
    357 
    358     // getSuperRegClasses - Returns a bit vector of all register classes
    359     // containing only SubIdx super-registers of this class.
    360     void getSuperRegClasses(const CodeGenSubRegIndex *SubIdx,
    361                             BitVector &Out) const;
    362 
    363     // addSuperRegClass - Add a class containing only SudIdx super-registers.
    364     void addSuperRegClass(CodeGenSubRegIndex *SubIdx,
    365                           CodeGenRegisterClass *SuperRC) {
    366       SuperRegClasses[SubIdx].insert(SuperRC);
    367     }
    368 
    369     // getSubClasses - Returns a constant BitVector of subclasses indexed by
    370     // EnumValue.
    371     // The SubClasses vector includes an entry for this class.
    372     const BitVector &getSubClasses() const { return SubClasses; }
    373 
    374     // getSuperClasses - Returns a list of super classes ordered by EnumValue.
    375     // The array does not include an entry for this class.
    376     ArrayRef<CodeGenRegisterClass*> getSuperClasses() const {
    377       return SuperClasses;
    378     }
    379 
    380     // Returns an ordered list of class members.
    381     // The order of registers is the same as in the .td file.
    382     // No = 0 is the default allocation order, No = 1 is the first alternative.
    383     ArrayRef<Record*> getOrder(unsigned No = 0) const {
    384         return Orders[No];
    385     }
    386 
    387     // Return the total number of allocation orders available.
    388     unsigned getNumOrders() const { return Orders.size(); }
    389 
    390     // Get the set of registers.  This set contains the same registers as
    391     // getOrder(0).
    392     const CodeGenRegister::Vec &getMembers() const { return Members; }
    393 
    394     // Get a bit vector of TopoSigs present in this register class.
    395     const BitVector &getTopoSigs() const { return TopoSigs; }
    396 
    397     // Populate a unique sorted list of units from a register set.
    398     void buildRegUnitSet(std::vector<unsigned> &RegUnits) const;
    399 
    400     CodeGenRegisterClass(CodeGenRegBank&, Record *R);
    401 
    402     // A key representing the parts of a register class used for forming
    403     // sub-classes.  Note the ordering provided by this key is not the same as
    404     // the topological order used for the EnumValues.
    405     struct Key {
    406       const CodeGenRegister::Vec *Members;
    407       unsigned SpillSize;
    408       unsigned SpillAlignment;
    409 
    410       Key(const CodeGenRegister::Vec *M, unsigned S = 0, unsigned A = 0)
    411         : Members(M), SpillSize(S), SpillAlignment(A) {}
    412 
    413       Key(const CodeGenRegisterClass &RC)
    414         : Members(&RC.getMembers()),
    415           SpillSize(RC.SpillSize),
    416           SpillAlignment(RC.SpillAlignment) {}
    417 
    418       // Lexicographical order of (Members, SpillSize, SpillAlignment).
    419       bool operator<(const Key&) const;
    420     };
    421 
    422     // Create a non-user defined register class.
    423     CodeGenRegisterClass(CodeGenRegBank&, StringRef Name, Key Props);
    424 
    425     // Called by CodeGenRegBank::CodeGenRegBank().
    426     static void computeSubClasses(CodeGenRegBank&);
    427   };
    428 
    429   // Register units are used to model interference and register pressure.
    430   // Every register is assigned one or more register units such that two
    431   // registers overlap if and only if they have a register unit in common.
    432   //
    433   // Normally, one register unit is created per leaf register. Non-leaf
    434   // registers inherit the units of their sub-registers.
    435   struct RegUnit {
    436     // Weight assigned to this RegUnit for estimating register pressure.
    437     // This is useful when equalizing weights in register classes with mixed
    438     // register topologies.
    439     unsigned Weight;
    440 
    441     // Each native RegUnit corresponds to one or two root registers. The full
    442     // set of registers containing this unit can be computed as the union of
    443     // these two registers and their super-registers.
    444     const CodeGenRegister *Roots[2];
    445 
    446     // Index into RegClassUnitSets where we can find the list of UnitSets that
    447     // contain this unit.
    448     unsigned RegClassUnitSetsIdx;
    449 
    450     RegUnit() : Weight(0), RegClassUnitSetsIdx(0) {
    451       Roots[0] = Roots[1] = nullptr;
    452     }
    453 
    454     ArrayRef<const CodeGenRegister*> getRoots() const {
    455       assert(!(Roots[1] && !Roots[0]) && "Invalid roots array");
    456       return makeArrayRef(Roots, !!Roots[0] + !!Roots[1]);
    457     }
    458   };
    459 
    460   // Each RegUnitSet is a sorted vector with a name.
    461   struct RegUnitSet {
    462     typedef std::vector<unsigned>::const_iterator iterator;
    463 
    464     std::string Name;
    465     std::vector<unsigned> Units;
    466     unsigned Weight; // Cache the sum of all unit weights.
    467     unsigned Order;  // Cache the sort key.
    468 
    469     RegUnitSet() : Weight(0), Order(0) {}
    470   };
    471 
    472   // Base vector for identifying TopoSigs. The contents uniquely identify a
    473   // TopoSig, only computeSuperRegs needs to know how.
    474   typedef SmallVector<unsigned, 16> TopoSigId;
    475 
    476   // CodeGenRegBank - Represent a target's registers and the relations between
    477   // them.
    478   class CodeGenRegBank {
    479     SetTheory Sets;
    480 
    481     std::deque<CodeGenSubRegIndex> SubRegIndices;
    482     DenseMap<Record*, CodeGenSubRegIndex*> Def2SubRegIdx;
    483 
    484     CodeGenSubRegIndex *createSubRegIndex(StringRef Name, StringRef NameSpace);
    485 
    486     typedef std::map<SmallVector<CodeGenSubRegIndex*, 8>,
    487                      CodeGenSubRegIndex*> ConcatIdxMap;
    488     ConcatIdxMap ConcatIdx;
    489 
    490     // Registers.
    491     std::deque<CodeGenRegister> Registers;
    492     StringMap<CodeGenRegister*> RegistersByName;
    493     DenseMap<Record*, CodeGenRegister*> Def2Reg;
    494     unsigned NumNativeRegUnits;
    495 
    496     std::map<TopoSigId, unsigned> TopoSigs;
    497 
    498     // Includes native (0..NumNativeRegUnits-1) and adopted register units.
    499     SmallVector<RegUnit, 8> RegUnits;
    500 
    501     // Register classes.
    502     std::list<CodeGenRegisterClass> RegClasses;
    503     DenseMap<Record*, CodeGenRegisterClass*> Def2RC;
    504     typedef std::map<CodeGenRegisterClass::Key, CodeGenRegisterClass*> RCKeyMap;
    505     RCKeyMap Key2RC;
    506 
    507     // Remember each unique set of register units. Initially, this contains a
    508     // unique set for each register class. Simliar sets are coalesced with
    509     // pruneUnitSets and new supersets are inferred during computeRegUnitSets.
    510     std::vector<RegUnitSet> RegUnitSets;
    511 
    512     // Map RegisterClass index to the index of the RegUnitSet that contains the
    513     // class's units and any inferred RegUnit supersets.
    514     //
    515     // NOTE: This could grow beyond the number of register classes when we map
    516     // register units to lists of unit sets. If the list of unit sets does not
    517     // already exist for a register class, we create a new entry in this vector.
    518     std::vector<std::vector<unsigned> > RegClassUnitSets;
    519 
    520     // Give each register unit set an order based on sorting criteria.
    521     std::vector<unsigned> RegUnitSetOrder;
    522 
    523     // Add RC to *2RC maps.
    524     void addToMaps(CodeGenRegisterClass*);
    525 
    526     // Create a synthetic sub-class if it is missing.
    527     CodeGenRegisterClass *getOrCreateSubClass(const CodeGenRegisterClass *RC,
    528                                               const CodeGenRegister::Vec *Membs,
    529                                               StringRef Name);
    530 
    531     // Infer missing register classes.
    532     void computeInferredRegisterClasses();
    533     void inferCommonSubClass(CodeGenRegisterClass *RC);
    534     void inferSubClassWithSubReg(CodeGenRegisterClass *RC);
    535     void inferMatchingSuperRegClass(CodeGenRegisterClass *RC) {
    536       inferMatchingSuperRegClass(RC, RegClasses.begin());
    537     }
    538 
    539     void inferMatchingSuperRegClass(
    540         CodeGenRegisterClass *RC,
    541         std::list<CodeGenRegisterClass>::iterator FirstSubRegRC);
    542 
    543     // Iteratively prune unit sets.
    544     void pruneUnitSets();
    545 
    546     // Compute a weight for each register unit created during getSubRegs.
    547     void computeRegUnitWeights();
    548 
    549     // Create a RegUnitSet for each RegClass and infer superclasses.
    550     void computeRegUnitSets();
    551 
    552     // Populate the Composite map from sub-register relationships.
    553     void computeComposites();
    554 
    555     // Compute a lane mask for each sub-register index.
    556     void computeSubRegLaneMasks();
    557 
    558     /// Computes a lane mask for each register unit enumerated by a physical
    559     /// register.
    560     void computeRegUnitLaneMasks();
    561 
    562   public:
    563     CodeGenRegBank(RecordKeeper&);
    564 
    565     SetTheory &getSets() { return Sets; }
    566 
    567     // Sub-register indices. The first NumNamedIndices are defined by the user
    568     // in the .td files. The rest are synthesized such that all sub-registers
    569     // have a unique name.
    570     const std::deque<CodeGenSubRegIndex> &getSubRegIndices() const {
    571       return SubRegIndices;
    572     }
    573 
    574     // Find a SubRegIndex form its Record def.
    575     CodeGenSubRegIndex *getSubRegIdx(Record*);
    576 
    577     // Find or create a sub-register index representing the A+B composition.
    578     CodeGenSubRegIndex *getCompositeSubRegIndex(CodeGenSubRegIndex *A,
    579                                                 CodeGenSubRegIndex *B);
    580 
    581     // Find or create a sub-register index representing the concatenation of
    582     // non-overlapping sibling indices.
    583     CodeGenSubRegIndex *
    584       getConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex *, 8>&);
    585 
    586     void
    587     addConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex *, 8> &Parts,
    588                          CodeGenSubRegIndex *Idx) {
    589       ConcatIdx.insert(std::make_pair(Parts, Idx));
    590     }
    591 
    592     const std::deque<CodeGenRegister> &getRegisters() { return Registers; }
    593     const StringMap<CodeGenRegister*> &getRegistersByName() {
    594       return RegistersByName;
    595     }
    596 
    597     // Find a register from its Record def.
    598     CodeGenRegister *getReg(Record*);
    599 
    600     // Get a Register's index into the Registers array.
    601     unsigned getRegIndex(const CodeGenRegister *Reg) const {
    602       return Reg->EnumValue - 1;
    603     }
    604 
    605     // Return the number of allocated TopoSigs. The first TopoSig representing
    606     // leaf registers is allocated number 0.
    607     unsigned getNumTopoSigs() const {
    608       return TopoSigs.size();
    609     }
    610 
    611     // Find or create a TopoSig for the given TopoSigId.
    612     // This function is only for use by CodeGenRegister::computeSuperRegs().
    613     // Others should simply use Reg->getTopoSig().
    614     unsigned getTopoSig(const TopoSigId &Id) {
    615       return TopoSigs.insert(std::make_pair(Id, TopoSigs.size())).first->second;
    616     }
    617 
    618     // Create a native register unit that is associated with one or two root
    619     // registers.
    620     unsigned newRegUnit(CodeGenRegister *R0, CodeGenRegister *R1 = nullptr) {
    621       RegUnits.resize(RegUnits.size() + 1);
    622       RegUnits.back().Roots[0] = R0;
    623       RegUnits.back().Roots[1] = R1;
    624       return RegUnits.size() - 1;
    625     }
    626 
    627     // Create a new non-native register unit that can be adopted by a register
    628     // to increase its pressure. Note that NumNativeRegUnits is not increased.
    629     unsigned newRegUnit(unsigned Weight) {
    630       RegUnits.resize(RegUnits.size() + 1);
    631       RegUnits.back().Weight = Weight;
    632       return RegUnits.size() - 1;
    633     }
    634 
    635     // Native units are the singular unit of a leaf register. Register aliasing
    636     // is completely characterized by native units. Adopted units exist to give
    637     // register additional weight but don't affect aliasing.
    638     bool isNativeUnit(unsigned RUID) {
    639       return RUID < NumNativeRegUnits;
    640     }
    641 
    642     unsigned getNumNativeRegUnits() const {
    643       return NumNativeRegUnits;
    644     }
    645 
    646     RegUnit &getRegUnit(unsigned RUID) { return RegUnits[RUID]; }
    647     const RegUnit &getRegUnit(unsigned RUID) const { return RegUnits[RUID]; }
    648 
    649     std::list<CodeGenRegisterClass> &getRegClasses() { return RegClasses; }
    650 
    651     const std::list<CodeGenRegisterClass> &getRegClasses() const {
    652       return RegClasses;
    653     }
    654 
    655     // Find a register class from its def.
    656     CodeGenRegisterClass *getRegClass(Record*);
    657 
    658     /// getRegisterClassForRegister - Find the register class that contains the
    659     /// specified physical register.  If the register is not in a register
    660     /// class, return null. If the register is in multiple classes, and the
    661     /// classes have a superset-subset relationship and the same set of types,
    662     /// return the superclass.  Otherwise return null.
    663     const CodeGenRegisterClass* getRegClassForRegister(Record *R);
    664 
    665     // Get the sum of unit weights.
    666     unsigned getRegUnitSetWeight(const std::vector<unsigned> &Units) const {
    667       unsigned Weight = 0;
    668       for (std::vector<unsigned>::const_iterator
    669              I = Units.begin(), E = Units.end(); I != E; ++I)
    670         Weight += getRegUnit(*I).Weight;
    671       return Weight;
    672     }
    673 
    674     unsigned getRegSetIDAt(unsigned Order) const {
    675       return RegUnitSetOrder[Order];
    676     }
    677     const RegUnitSet &getRegSetAt(unsigned Order) const {
    678       return RegUnitSets[RegUnitSetOrder[Order]];
    679     }
    680 
    681     // Increase a RegUnitWeight.
    682     void increaseRegUnitWeight(unsigned RUID, unsigned Inc) {
    683       getRegUnit(RUID).Weight += Inc;
    684     }
    685 
    686     // Get the number of register pressure dimensions.
    687     unsigned getNumRegPressureSets() const { return RegUnitSets.size(); }
    688 
    689     // Get a set of register unit IDs for a given dimension of pressure.
    690     const RegUnitSet &getRegPressureSet(unsigned Idx) const {
    691       return RegUnitSets[Idx];
    692     }
    693 
    694     // The number of pressure set lists may be larget than the number of
    695     // register classes if some register units appeared in a list of sets that
    696     // did not correspond to an existing register class.
    697     unsigned getNumRegClassPressureSetLists() const {
    698       return RegClassUnitSets.size();
    699     }
    700 
    701     // Get a list of pressure set IDs for a register class. Liveness of a
    702     // register in this class impacts each pressure set in this list by the
    703     // weight of the register. An exact solution requires all registers in a
    704     // class to have the same class, but it is not strictly guaranteed.
    705     ArrayRef<unsigned> getRCPressureSetIDs(unsigned RCIdx) const {
    706       return RegClassUnitSets[RCIdx];
    707     }
    708 
    709     // Computed derived records such as missing sub-register indices.
    710     void computeDerivedInfo();
    711 
    712     // Compute the set of registers completely covered by the registers in Regs.
    713     // The returned BitVector will have a bit set for each register in Regs,
    714     // all sub-registers, and all super-registers that are covered by the
    715     // registers in Regs.
    716     //
    717     // This is used to compute the mask of call-preserved registers from a list
    718     // of callee-saves.
    719     BitVector computeCoveredRegisters(ArrayRef<Record*> Regs);
    720 
    721     // Bit mask of lanes that cover their registers. A sub-register index whose
    722     // LaneMask is contained in CoveringLanes will be completely covered by
    723     // another sub-register with the same or larger lane mask.
    724     unsigned CoveringLanes;
    725   };
    726 }
    727 
    728 #endif
    729