| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86InstComments.cpp | 26 /// number in the SrcVT type is expanded to fill the src xmm register and the
28 static void getZeroExtensionTypes(const MCInst *MI, MVT &SrcVT, MVT &DstVT) {
37 SrcVT = MVT::v16i8;
42 SrcVT = MVT::v16i8;
49 SrcVT = MVT::v16i8;
54 SrcVT = MVT::v16i8;
61 SrcVT = MVT::v16i8;
66 SrcVT = MVT::v16i8;
74 SrcVT = MVT::v8i16;
79 SrcVT = MVT::v8i16;
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86SelectionDAGInfo.cpp | 278 EVT SrcVT = Src.getValueType();
283 DAG.getNode(ISD::ADD, dl, SrcVT, Src,
284 DAG.getConstant(Offset, SrcVT)),
|
| X86ISelDAGToDAG.cpp | 505 MVT SrcVT = N->getOperand(0).getSimpleValueType();
509 if (SrcVT.isVector() || DstVT.isVector())
516 bool SrcIsSSE = X86Lowering->isScalarFPTypeInSSEReg(SrcVT);
537 MemVT = SrcIsSSE ? SrcVT : DstVT;
[all...] |
| X86FastISel.cpp | 95 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
520 /// type SrcVT to type DstVT using the specified extension opcode Opc (e.g.
523 unsigned Src, EVT SrcVT,
525 unsigned RR = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc,
[all...] |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| Scalarizer.cpp | 483 VectorType *SrcVT = dyn_cast<VectorType>(BCI.getSrcTy());
484 if (!DstVT || !SrcVT)
488 unsigned SrcNumElems = SrcVT->getNumElements();
520 Type *MidTy = VectorType::get(SrcVT->getElementType(), FanIn);
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 482 EVT SrcVT = LD->getMemoryVT();
487 unsigned NumElem = SrcVT.getVectorNumElements();
489 EVT SrcEltVT = SrcVT.getScalarType();
492 if (SrcVT.getVectorNumElements() > 1 && !SrcEltVT.isByteSized()) {
508 unsigned RemainingBytes = SrcVT.getStoreSize();
596 unsigned Stride = SrcVT.getScalarType().getSizeInBits()/8;
602 SrcVT.getScalarType(),
787 EVT SrcVT = Src.getValueType();
788 int NumSrcElements = SrcVT.getVectorNumElements();
802 DAG.getVectorShuffle(SrcVT, DL, Src, DAG.getUNDEF(SrcVT), ShuffleMask))
[all...] |
| FastISel.cpp | [all...] |
| LegalizeFloatTypes.cpp | [all...] |
| SelectionDAGISel.cpp | 647 EVT SrcVT = Src.getValueType();
648 if (!SrcVT.isInteger() || SrcVT.isVector())
[all...] |
| LegalizeIntegerTypes.cpp | [all...] |
| LegalizeVectorTypes.cpp | [all...] |
| DAGCombiner.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsFastISel.cpp | 120 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
121 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
124 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
126 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
127 bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
129 bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
854 EVT SrcVT = TLI.getValueType(Src->getType(), true);
857 if (SrcVT != MVT::f32 || DestVT != MVT::f64)
877 EVT SrcVT = TLI.getValueType(Src->getType(), true);
880 if (SrcVT != MVT::f64 || DestVT != MVT::f32
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | 350 EVT SrcVT;
352 SrcVT = cast<VTSDNode>(N.getOperand(1))->getVT();
354 SrcVT = N.getOperand(0).getValueType();
356 if (!IsLoadStore && SrcVT == MVT::i8)
358 else if (!IsLoadStore && SrcVT == MVT::i16)
360 else if (SrcVT == MVT::i32)
362 assert(SrcVT != MVT::i64 && "extend from 64-bits?");
367 EVT SrcVT = N.getOperand(0).getValueType();
368 if (!IsLoadStore && SrcVT == MVT::i8)
370 else if (!IsLoadStore && SrcVT == MVT::i16
[all...] |
| AArch64FastISel.cpp | 153 bool optimizeIntExtLoad(const Instruction *I, MVT RetVT, MVT SrcVT);
188 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
219 unsigned emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
223 unsigned emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
227 unsigned emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
[all...] |
| AArch64ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCFastISel.cpp | 159 bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
783 MVT SrcVT = SrcEVT.getSimpleVT();
785 if (SrcVT == MVT::i1 && PPCSubTarget->useCRBits())
798 if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 ||
799 SrcVT == MVT::i8 || SrcVT == MVT::i1) {
809 switch (SrcVT.SimpleTy) {
849 if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt)
[all...] |
| /external/llvm/lib/Target/R600/ |
| AMDGPUISelDAGToDAG.cpp | [all...] |
| SIISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMFastISel.cpp | 183 unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
[all...] |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| CodeGenPrepare.cpp | 722 EVT SrcVT = TLI.getValueType(CI->getOperand(0)->getType());
726 if (SrcVT.isInteger() != DstVT.isInteger())
731 if (SrcVT.bitsLT(DstVT)) return false;
736 if (TLI.getTypeAction(CI->getContext(), SrcVT) ==
738 SrcVT = TLI.getTypeToTransformTo(CI->getContext(), SrcVT);
744 if (SrcVT != DstVT)
[all...] |
