1 //===-- X86BaseInfo.h - Top level definitions for X86 -------- --*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains small standalone helper functions and enum definitions for 11 // the X86 target useful for the compiler back-end and the MC libraries. 12 // As such, it deliberately does not include references to LLVM core 13 // code gen types, passes, etc.. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #ifndef LLVM_LIB_TARGET_X86_MCTARGETDESC_X86BASEINFO_H 18 #define LLVM_LIB_TARGET_X86_MCTARGETDESC_X86BASEINFO_H 19 20 #include "X86MCTargetDesc.h" 21 #include "llvm/MC/MCInstrDesc.h" 22 #include "llvm/Support/DataTypes.h" 23 #include "llvm/Support/ErrorHandling.h" 24 25 namespace llvm { 26 27 namespace X86 { 28 // Enums for memory operand decoding. Each memory operand is represented with 29 // a 5 operand sequence in the form: 30 // [BaseReg, ScaleAmt, IndexReg, Disp, Segment] 31 // These enums help decode this. 32 enum { 33 AddrBaseReg = 0, 34 AddrScaleAmt = 1, 35 AddrIndexReg = 2, 36 AddrDisp = 3, 37 38 /// AddrSegmentReg - The operand # of the segment in the memory operand. 39 AddrSegmentReg = 4, 40 41 /// AddrNumOperands - Total number of operands in a memory reference. 42 AddrNumOperands = 5 43 }; 44 } // end namespace X86; 45 46 /// X86II - This namespace holds all of the target specific flags that 47 /// instruction info tracks. 48 /// 49 namespace X86II { 50 /// Target Operand Flag enum. 51 enum TOF { 52 //===------------------------------------------------------------------===// 53 // X86 Specific MachineOperand flags. 54 55 MO_NO_FLAG, 56 57 /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a 58 /// relocation of: 59 /// SYMBOL_LABEL + [. - PICBASELABEL] 60 MO_GOT_ABSOLUTE_ADDRESS, 61 62 /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the 63 /// immediate should get the value of the symbol minus the PIC base label: 64 /// SYMBOL_LABEL - PICBASELABEL 65 MO_PIC_BASE_OFFSET, 66 67 /// MO_GOT - On a symbol operand this indicates that the immediate is the 68 /// offset to the GOT entry for the symbol name from the base of the GOT. 69 /// 70 /// See the X86-64 ELF ABI supplement for more details. 71 /// SYMBOL_LABEL @GOT 72 MO_GOT, 73 74 /// MO_GOTOFF - On a symbol operand this indicates that the immediate is 75 /// the offset to the location of the symbol name from the base of the GOT. 76 /// 77 /// See the X86-64 ELF ABI supplement for more details. 78 /// SYMBOL_LABEL @GOTOFF 79 MO_GOTOFF, 80 81 /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is 82 /// offset to the GOT entry for the symbol name from the current code 83 /// location. 84 /// 85 /// See the X86-64 ELF ABI supplement for more details. 86 /// SYMBOL_LABEL @GOTPCREL 87 MO_GOTPCREL, 88 89 /// MO_PLT - On a symbol operand this indicates that the immediate is 90 /// offset to the PLT entry of symbol name from the current code location. 91 /// 92 /// See the X86-64 ELF ABI supplement for more details. 93 /// SYMBOL_LABEL @PLT 94 MO_PLT, 95 96 /// MO_TLSGD - On a symbol operand this indicates that the immediate is 97 /// the offset of the GOT entry with the TLS index structure that contains 98 /// the module number and variable offset for the symbol. Used in the 99 /// general dynamic TLS access model. 100 /// 101 /// See 'ELF Handling for Thread-Local Storage' for more details. 102 /// SYMBOL_LABEL @TLSGD 103 MO_TLSGD, 104 105 /// MO_TLSLD - On a symbol operand this indicates that the immediate is 106 /// the offset of the GOT entry with the TLS index for the module that 107 /// contains the symbol. When this index is passed to a call to 108 /// __tls_get_addr, the function will return the base address of the TLS 109 /// block for the symbol. Used in the x86-64 local dynamic TLS access model. 110 /// 111 /// See 'ELF Handling for Thread-Local Storage' for more details. 112 /// SYMBOL_LABEL @TLSLD 113 MO_TLSLD, 114 115 /// MO_TLSLDM - On a symbol operand this indicates that the immediate is 116 /// the offset of the GOT entry with the TLS index for the module that 117 /// contains the symbol. When this index is passed to a call to 118 /// ___tls_get_addr, the function will return the base address of the TLS 119 /// block for the symbol. Used in the IA32 local dynamic TLS access model. 120 /// 121 /// See 'ELF Handling for Thread-Local Storage' for more details. 122 /// SYMBOL_LABEL @TLSLDM 123 MO_TLSLDM, 124 125 /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is 126 /// the offset of the GOT entry with the thread-pointer offset for the 127 /// symbol. Used in the x86-64 initial exec TLS access model. 128 /// 129 /// See 'ELF Handling for Thread-Local Storage' for more details. 130 /// SYMBOL_LABEL @GOTTPOFF 131 MO_GOTTPOFF, 132 133 /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is 134 /// the absolute address of the GOT entry with the negative thread-pointer 135 /// offset for the symbol. Used in the non-PIC IA32 initial exec TLS access 136 /// model. 137 /// 138 /// See 'ELF Handling for Thread-Local Storage' for more details. 139 /// SYMBOL_LABEL @INDNTPOFF 140 MO_INDNTPOFF, 141 142 /// MO_TPOFF - On a symbol operand this indicates that the immediate is 143 /// the thread-pointer offset for the symbol. Used in the x86-64 local 144 /// exec TLS access model. 145 /// 146 /// See 'ELF Handling for Thread-Local Storage' for more details. 147 /// SYMBOL_LABEL @TPOFF 148 MO_TPOFF, 149 150 /// MO_DTPOFF - On a symbol operand this indicates that the immediate is 151 /// the offset of the GOT entry with the TLS offset of the symbol. Used 152 /// in the local dynamic TLS access model. 153 /// 154 /// See 'ELF Handling for Thread-Local Storage' for more details. 155 /// SYMBOL_LABEL @DTPOFF 156 MO_DTPOFF, 157 158 /// MO_NTPOFF - On a symbol operand this indicates that the immediate is 159 /// the negative thread-pointer offset for the symbol. Used in the IA32 160 /// local exec TLS access model. 161 /// 162 /// See 'ELF Handling for Thread-Local Storage' for more details. 163 /// SYMBOL_LABEL @NTPOFF 164 MO_NTPOFF, 165 166 /// MO_GOTNTPOFF - On a symbol operand this indicates that the immediate is 167 /// the offset of the GOT entry with the negative thread-pointer offset for 168 /// the symbol. Used in the PIC IA32 initial exec TLS access model. 169 /// 170 /// See 'ELF Handling for Thread-Local Storage' for more details. 171 /// SYMBOL_LABEL @GOTNTPOFF 172 MO_GOTNTPOFF, 173 174 /// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the 175 /// reference is actually to the "__imp_FOO" symbol. This is used for 176 /// dllimport linkage on windows. 177 MO_DLLIMPORT, 178 179 /// MO_DARWIN_STUB - On a symbol operand "FOO", this indicates that the 180 /// reference is actually to the "FOO$stub" symbol. This is used for calls 181 /// and jumps to external functions on Tiger and earlier. 182 MO_DARWIN_STUB, 183 184 /// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the 185 /// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a 186 /// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub. 187 MO_DARWIN_NONLAZY, 188 189 /// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates 190 /// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is 191 /// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub. 192 MO_DARWIN_NONLAZY_PIC_BASE, 193 194 /// MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this 195 /// indicates that the reference is actually to "FOO$non_lazy_ptr -PICBASE", 196 /// which is a PIC-base-relative reference to a hidden dyld lazy pointer 197 /// stub. 198 MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE, 199 200 /// MO_TLVP - On a symbol operand this indicates that the immediate is 201 /// some TLS offset. 202 /// 203 /// This is the TLS offset for the Darwin TLS mechanism. 204 MO_TLVP, 205 206 /// MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate 207 /// is some TLS offset from the picbase. 208 /// 209 /// This is the 32-bit TLS offset for Darwin TLS in PIC mode. 210 MO_TLVP_PIC_BASE, 211 212 /// MO_SECREL - On a symbol operand this indicates that the immediate is 213 /// the offset from beginning of section. 214 /// 215 /// This is the TLS offset for the COFF/Windows TLS mechanism. 216 MO_SECREL 217 }; 218 219 enum : uint64_t { 220 //===------------------------------------------------------------------===// 221 // Instruction encodings. These are the standard/most common forms for X86 222 // instructions. 223 // 224 225 // PseudoFrm - This represents an instruction that is a pseudo instruction 226 // or one that has not been implemented yet. It is illegal to code generate 227 // it, but tolerated for intermediate implementation stages. 228 Pseudo = 0, 229 230 /// Raw - This form is for instructions that don't have any operands, so 231 /// they are just a fixed opcode value, like 'leave'. 232 RawFrm = 1, 233 234 /// AddRegFrm - This form is used for instructions like 'push r32' that have 235 /// their one register operand added to their opcode. 236 AddRegFrm = 2, 237 238 /// MRMDestReg - This form is used for instructions that use the Mod/RM byte 239 /// to specify a destination, which in this case is a register. 240 /// 241 MRMDestReg = 3, 242 243 /// MRMDestMem - This form is used for instructions that use the Mod/RM byte 244 /// to specify a destination, which in this case is memory. 245 /// 246 MRMDestMem = 4, 247 248 /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte 249 /// to specify a source, which in this case is a register. 250 /// 251 MRMSrcReg = 5, 252 253 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte 254 /// to specify a source, which in this case is memory. 255 /// 256 MRMSrcMem = 6, 257 258 /// RawFrmMemOffs - This form is for instructions that store an absolute 259 /// memory offset as an immediate with a possible segment override. 260 RawFrmMemOffs = 7, 261 262 /// RawFrmSrc - This form is for instructions that use the source index 263 /// register SI/ESI/RSI with a possible segment override. 264 RawFrmSrc = 8, 265 266 /// RawFrmDst - This form is for instructions that use the destination index 267 /// register DI/EDI/ESI. 268 RawFrmDst = 9, 269 270 /// RawFrmSrc - This form is for instructions that use the the source index 271 /// register SI/ESI/ERI with a possible segment override, and also the 272 /// destination index register DI/ESI/RDI. 273 RawFrmDstSrc = 10, 274 275 /// RawFrmImm8 - This is used for the ENTER instruction, which has two 276 /// immediates, the first of which is a 16-bit immediate (specified by 277 /// the imm encoding) and the second is a 8-bit fixed value. 278 RawFrmImm8 = 11, 279 280 /// RawFrmImm16 - This is used for CALL FAR instructions, which have two 281 /// immediates, the first of which is a 16 or 32-bit immediate (specified by 282 /// the imm encoding) and the second is a 16-bit fixed value. In the AMD 283 /// manual, this operand is described as pntr16:32 and pntr16:16 284 RawFrmImm16 = 12, 285 286 /// MRMX[rm] - The forms are used to represent instructions that use a 287 /// Mod/RM byte, and don't use the middle field for anything. 288 MRMXr = 14, MRMXm = 15, 289 290 /// MRM[0-7][rm] - These forms are used to represent instructions that use 291 /// a Mod/RM byte, and use the middle field to hold extended opcode 292 /// information. In the intel manual these are represented as /0, /1, ... 293 /// 294 295 // First, instructions that operate on a register r/m operand... 296 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 297 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 298 299 // Next, instructions that operate on a memory r/m operand... 300 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3 301 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7 302 303 //// MRM_XX - A mod/rm byte of exactly 0xXX. 304 MRM_C0 = 32, MRM_C1 = 33, MRM_C2 = 34, MRM_C3 = 35, 305 MRM_C4 = 36, MRM_C5 = 37, MRM_C6 = 38, MRM_C7 = 39, 306 MRM_C8 = 40, MRM_C9 = 41, MRM_CA = 42, MRM_CB = 43, 307 MRM_CC = 44, MRM_CD = 45, MRM_CE = 46, MRM_CF = 47, 308 MRM_D0 = 48, MRM_D1 = 49, MRM_D2 = 50, MRM_D3 = 51, 309 MRM_D4 = 52, MRM_D5 = 53, MRM_D6 = 54, MRM_D7 = 55, 310 MRM_D8 = 56, MRM_D9 = 57, MRM_DA = 58, MRM_DB = 59, 311 MRM_DC = 60, MRM_DD = 61, MRM_DE = 62, MRM_DF = 63, 312 MRM_E0 = 64, MRM_E1 = 65, MRM_E2 = 66, MRM_E3 = 67, 313 MRM_E4 = 68, MRM_E5 = 69, MRM_E6 = 70, MRM_E7 = 71, 314 MRM_E8 = 72, MRM_E9 = 73, MRM_EA = 74, MRM_EB = 75, 315 MRM_EC = 76, MRM_ED = 77, MRM_EE = 78, MRM_EF = 79, 316 MRM_F0 = 80, MRM_F1 = 81, MRM_F2 = 82, MRM_F3 = 83, 317 MRM_F4 = 84, MRM_F5 = 85, MRM_F6 = 86, MRM_F7 = 87, 318 MRM_F8 = 88, MRM_F9 = 89, MRM_FA = 90, MRM_FB = 91, 319 MRM_FC = 92, MRM_FD = 93, MRM_FE = 94, MRM_FF = 95, 320 321 FormMask = 127, 322 323 //===------------------------------------------------------------------===// 324 // Actual flags... 325 326 // OpSize - OpSizeFixed implies instruction never needs a 0x66 prefix. 327 // OpSize16 means this is a 16-bit instruction and needs 0x66 prefix in 328 // 32-bit mode. OpSize32 means this is a 32-bit instruction needs a 0x66 329 // prefix in 16-bit mode. 330 OpSizeShift = 7, 331 OpSizeMask = 0x3 << OpSizeShift, 332 333 OpSizeFixed = 0 << OpSizeShift, 334 OpSize16 = 1 << OpSizeShift, 335 OpSize32 = 2 << OpSizeShift, 336 337 // AsSize - AdSizeX implies this instruction determines its need of 0x67 338 // prefix from a normal ModRM memory operand. The other types indicate that 339 // an operand is encoded with a specific width and a prefix is needed if 340 // it differs from the current mode. 341 AdSizeShift = OpSizeShift + 2, 342 AdSizeMask = 0x3 << AdSizeShift, 343 344 AdSizeX = 1 << AdSizeShift, 345 AdSize16 = 1 << AdSizeShift, 346 AdSize32 = 2 << AdSizeShift, 347 AdSize64 = 3 << AdSizeShift, 348 349 //===------------------------------------------------------------------===// 350 // OpPrefix - There are several prefix bytes that are used as opcode 351 // extensions. These are 0x66, 0xF3, and 0xF2. If this field is 0 there is 352 // no prefix. 353 // 354 OpPrefixShift = AdSizeShift + 2, 355 OpPrefixMask = 0x7 << OpPrefixShift, 356 357 // PS, PD - Prefix code for packed single and double precision vector 358 // floating point operations performed in the SSE registers. 359 PS = 1 << OpPrefixShift, PD = 2 << OpPrefixShift, 360 361 // XS, XD - These prefix codes are for single and double precision scalar 362 // floating point operations performed in the SSE registers. 363 XS = 3 << OpPrefixShift, XD = 4 << OpPrefixShift, 364 365 //===------------------------------------------------------------------===// 366 // OpMap - This field determines which opcode map this instruction 367 // belongs to. i.e. one-byte, two-byte, 0x0f 0x38, 0x0f 0x3a, etc. 368 // 369 OpMapShift = OpPrefixShift + 3, 370 OpMapMask = 0x7 << OpMapShift, 371 372 // OB - OneByte - Set if this instruction has a one byte opcode. 373 OB = 0 << OpMapShift, 374 375 // TB - TwoByte - Set if this instruction has a two byte opcode, which 376 // starts with a 0x0F byte before the real opcode. 377 TB = 1 << OpMapShift, 378 379 // T8, TA - Prefix after the 0x0F prefix. 380 T8 = 2 << OpMapShift, TA = 3 << OpMapShift, 381 382 // XOP8 - Prefix to include use of imm byte. 383 XOP8 = 4 << OpMapShift, 384 385 // XOP9 - Prefix to exclude use of imm byte. 386 XOP9 = 5 << OpMapShift, 387 388 // XOPA - Prefix to encode 0xA in VEX.MMMM of XOP instructions. 389 XOPA = 6 << OpMapShift, 390 391 //===------------------------------------------------------------------===// 392 // REX_W - REX prefixes are instruction prefixes used in 64-bit mode. 393 // They are used to specify GPRs and SSE registers, 64-bit operand size, 394 // etc. We only cares about REX.W and REX.R bits and only the former is 395 // statically determined. 396 // 397 REXShift = OpMapShift + 3, 398 REX_W = 1 << REXShift, 399 400 //===------------------------------------------------------------------===// 401 // This three-bit field describes the size of an immediate operand. Zero is 402 // unused so that we can tell if we forgot to set a value. 403 ImmShift = REXShift + 1, 404 ImmMask = 15 << ImmShift, 405 Imm8 = 1 << ImmShift, 406 Imm8PCRel = 2 << ImmShift, 407 Imm16 = 3 << ImmShift, 408 Imm16PCRel = 4 << ImmShift, 409 Imm32 = 5 << ImmShift, 410 Imm32PCRel = 6 << ImmShift, 411 Imm32S = 7 << ImmShift, 412 Imm64 = 8 << ImmShift, 413 414 //===------------------------------------------------------------------===// 415 // FP Instruction Classification... Zero is non-fp instruction. 416 417 // FPTypeMask - Mask for all of the FP types... 418 FPTypeShift = ImmShift + 4, 419 FPTypeMask = 7 << FPTypeShift, 420 421 // NotFP - The default, set for instructions that do not use FP registers. 422 NotFP = 0 << FPTypeShift, 423 424 // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0 425 ZeroArgFP = 1 << FPTypeShift, 426 427 // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst 428 OneArgFP = 2 << FPTypeShift, 429 430 // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a 431 // result back to ST(0). For example, fcos, fsqrt, etc. 432 // 433 OneArgFPRW = 3 << FPTypeShift, 434 435 // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an 436 // explicit argument, storing the result to either ST(0) or the implicit 437 // argument. For example: fadd, fsub, fmul, etc... 438 TwoArgFP = 4 << FPTypeShift, 439 440 // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an 441 // explicit argument, but have no destination. Example: fucom, fucomi, ... 442 CompareFP = 5 << FPTypeShift, 443 444 // CondMovFP - "2 operand" floating point conditional move instructions. 445 CondMovFP = 6 << FPTypeShift, 446 447 // SpecialFP - Special instruction forms. Dispatch by opcode explicitly. 448 SpecialFP = 7 << FPTypeShift, 449 450 // Lock prefix 451 LOCKShift = FPTypeShift + 3, 452 LOCK = 1 << LOCKShift, 453 454 // REP prefix 455 REPShift = LOCKShift + 1, 456 REP = 1 << REPShift, 457 458 // Execution domain for SSE instructions. 459 // 0 means normal, non-SSE instruction. 460 SSEDomainShift = REPShift + 1, 461 462 // Encoding 463 EncodingShift = SSEDomainShift + 2, 464 EncodingMask = 0x3 << EncodingShift, 465 466 // VEX - encoding using 0xC4/0xC5 467 VEX = 1 << EncodingShift, 468 469 /// XOP - Opcode prefix used by XOP instructions. 470 XOP = 2 << EncodingShift, 471 472 // VEX_EVEX - Specifies that this instruction use EVEX form which provides 473 // syntax support up to 32 512-bit register operands and up to 7 16-bit 474 // mask operands as well as source operand data swizzling/memory operand 475 // conversion, eviction hint, and rounding mode. 476 EVEX = 3 << EncodingShift, 477 478 // Opcode 479 OpcodeShift = EncodingShift + 2, 480 481 /// VEX_W - Has a opcode specific functionality, but is used in the same 482 /// way as REX_W is for regular SSE instructions. 483 VEX_WShift = OpcodeShift + 8, 484 VEX_W = 1ULL << VEX_WShift, 485 486 /// VEX_4V - Used to specify an additional AVX/SSE register. Several 2 487 /// address instructions in SSE are represented as 3 address ones in AVX 488 /// and the additional register is encoded in VEX_VVVV prefix. 489 VEX_4VShift = VEX_WShift + 1, 490 VEX_4V = 1ULL << VEX_4VShift, 491 492 /// VEX_4VOp3 - Similar to VEX_4V, but used on instructions that encode 493 /// operand 3 with VEX.vvvv. 494 VEX_4VOp3Shift = VEX_4VShift + 1, 495 VEX_4VOp3 = 1ULL << VEX_4VOp3Shift, 496 497 /// VEX_I8IMM - Specifies that the last register used in a AVX instruction, 498 /// must be encoded in the i8 immediate field. This usually happens in 499 /// instructions with 4 operands. 500 VEX_I8IMMShift = VEX_4VOp3Shift + 1, 501 VEX_I8IMM = 1ULL << VEX_I8IMMShift, 502 503 /// VEX_L - Stands for a bit in the VEX opcode prefix meaning the current 504 /// instruction uses 256-bit wide registers. This is usually auto detected 505 /// if a VR256 register is used, but some AVX instructions also have this 506 /// field marked when using a f256 memory references. 507 VEX_LShift = VEX_I8IMMShift + 1, 508 VEX_L = 1ULL << VEX_LShift, 509 510 // VEX_LIG - Specifies that this instruction ignores the L-bit in the VEX 511 // prefix. Usually used for scalar instructions. Needed by disassembler. 512 VEX_LIGShift = VEX_LShift + 1, 513 VEX_LIG = 1ULL << VEX_LIGShift, 514 515 // TODO: we should combine VEX_L and VEX_LIG together to form a 2-bit field 516 // with following encoding: 517 // - 00 V128 518 // - 01 V256 519 // - 10 V512 520 // - 11 LIG (but, in insn encoding, leave VEX.L and EVEX.L in zeros. 521 // this will save 1 tsflag bit 522 523 // EVEX_K - Set if this instruction requires masking 524 EVEX_KShift = VEX_LIGShift + 1, 525 EVEX_K = 1ULL << EVEX_KShift, 526 527 // EVEX_Z - Set if this instruction has EVEX.Z field set. 528 EVEX_ZShift = EVEX_KShift + 1, 529 EVEX_Z = 1ULL << EVEX_ZShift, 530 531 // EVEX_L2 - Set if this instruction has EVEX.L' field set. 532 EVEX_L2Shift = EVEX_ZShift + 1, 533 EVEX_L2 = 1ULL << EVEX_L2Shift, 534 535 // EVEX_B - Set if this instruction has EVEX.B field set. 536 EVEX_BShift = EVEX_L2Shift + 1, 537 EVEX_B = 1ULL << EVEX_BShift, 538 539 // The scaling factor for the AVX512's 8-bit compressed displacement. 540 CD8_Scale_Shift = EVEX_BShift + 1, 541 CD8_Scale_Mask = 127ULL << CD8_Scale_Shift, 542 543 /// Has3DNow0F0FOpcode - This flag indicates that the instruction uses the 544 /// wacky 0x0F 0x0F prefix for 3DNow! instructions. The manual documents 545 /// this as having a 0x0F prefix with a 0x0F opcode, and each instruction 546 /// storing a classifier in the imm8 field. To simplify our implementation, 547 /// we handle this by storeing the classifier in the opcode field and using 548 /// this flag to indicate that the encoder should do the wacky 3DNow! thing. 549 Has3DNow0F0FOpcodeShift = CD8_Scale_Shift + 7, 550 Has3DNow0F0FOpcode = 1ULL << Has3DNow0F0FOpcodeShift, 551 552 /// MemOp4 - Used to indicate swapping of operand 3 and 4 to be encoded in 553 /// ModRM or I8IMM. This is used for FMA4 and XOP instructions. 554 MemOp4Shift = Has3DNow0F0FOpcodeShift + 1, 555 MemOp4 = 1ULL << MemOp4Shift, 556 557 /// Explicitly specified rounding control 558 EVEX_RCShift = MemOp4Shift + 1, 559 EVEX_RC = 1ULL << EVEX_RCShift 560 }; 561 562 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the 563 // specified machine instruction. 564 // 565 inline unsigned char getBaseOpcodeFor(uint64_t TSFlags) { 566 return TSFlags >> X86II::OpcodeShift; 567 } 568 569 inline bool hasImm(uint64_t TSFlags) { 570 return (TSFlags & X86II::ImmMask) != 0; 571 } 572 573 /// getSizeOfImm - Decode the "size of immediate" field from the TSFlags field 574 /// of the specified instruction. 575 inline unsigned getSizeOfImm(uint64_t TSFlags) { 576 switch (TSFlags & X86II::ImmMask) { 577 default: llvm_unreachable("Unknown immediate size"); 578 case X86II::Imm8: 579 case X86II::Imm8PCRel: return 1; 580 case X86II::Imm16: 581 case X86II::Imm16PCRel: return 2; 582 case X86II::Imm32: 583 case X86II::Imm32S: 584 case X86II::Imm32PCRel: return 4; 585 case X86II::Imm64: return 8; 586 } 587 } 588 589 /// isImmPCRel - Return true if the immediate of the specified instruction's 590 /// TSFlags indicates that it is pc relative. 591 inline unsigned isImmPCRel(uint64_t TSFlags) { 592 switch (TSFlags & X86II::ImmMask) { 593 default: llvm_unreachable("Unknown immediate size"); 594 case X86II::Imm8PCRel: 595 case X86II::Imm16PCRel: 596 case X86II::Imm32PCRel: 597 return true; 598 case X86II::Imm8: 599 case X86II::Imm16: 600 case X86II::Imm32: 601 case X86II::Imm32S: 602 case X86II::Imm64: 603 return false; 604 } 605 } 606 607 /// isImmSigned - Return true if the immediate of the specified instruction's 608 /// TSFlags indicates that it is signed. 609 inline unsigned isImmSigned(uint64_t TSFlags) { 610 switch (TSFlags & X86II::ImmMask) { 611 default: llvm_unreachable("Unknown immediate signedness"); 612 case X86II::Imm32S: 613 return true; 614 case X86II::Imm8: 615 case X86II::Imm8PCRel: 616 case X86II::Imm16: 617 case X86II::Imm16PCRel: 618 case X86II::Imm32: 619 case X86II::Imm32PCRel: 620 case X86II::Imm64: 621 return false; 622 } 623 } 624 625 /// getOperandBias - compute any additional adjustment needed to 626 /// the offset to the start of the memory operand 627 /// in this instruction. 628 /// If this is a two-address instruction,skip one of the register operands. 629 /// FIXME: This should be handled during MCInst lowering. 630 inline int getOperandBias(const MCInstrDesc& Desc) 631 { 632 unsigned NumOps = Desc.getNumOperands(); 633 unsigned CurOp = 0; 634 if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) == 0) 635 ++CurOp; 636 else if (NumOps > 3 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 && 637 Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1) 638 // Special case for AVX-512 GATHER with 2 TIED_TO operands 639 // Skip the first 2 operands: dst, mask_wb 640 CurOp += 2; 641 else if (NumOps > 3 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 && 642 Desc.getOperandConstraint(NumOps - 1, MCOI::TIED_TO) == 1) 643 // Special case for GATHER with 2 TIED_TO operands 644 // Skip the first 2 operands: dst, mask_wb 645 CurOp += 2; 646 else if (NumOps > 2 && Desc.getOperandConstraint(NumOps - 2, MCOI::TIED_TO) == 0) 647 // SCATTER 648 ++CurOp; 649 return CurOp; 650 } 651 652 /// getMemoryOperandNo - The function returns the MCInst operand # for the 653 /// first field of the memory operand. If the instruction doesn't have a 654 /// memory operand, this returns -1. 655 /// 656 /// Note that this ignores tied operands. If there is a tied register which 657 /// is duplicated in the MCInst (e.g. "EAX = addl EAX, [mem]") it is only 658 /// counted as one operand. 659 /// 660 inline int getMemoryOperandNo(uint64_t TSFlags, unsigned Opcode) { 661 bool HasVEX_4V = TSFlags & X86II::VEX_4V; 662 bool HasMemOp4 = TSFlags & X86II::MemOp4; 663 bool HasEVEX_K = TSFlags & X86II::EVEX_K; 664 665 switch (TSFlags & X86II::FormMask) { 666 default: llvm_unreachable("Unknown FormMask value in getMemoryOperandNo!"); 667 case X86II::Pseudo: 668 case X86II::RawFrm: 669 case X86II::AddRegFrm: 670 case X86II::MRMDestReg: 671 case X86II::MRMSrcReg: 672 case X86II::RawFrmImm8: 673 case X86II::RawFrmImm16: 674 case X86II::RawFrmMemOffs: 675 case X86II::RawFrmSrc: 676 case X86II::RawFrmDst: 677 case X86II::RawFrmDstSrc: 678 return -1; 679 case X86II::MRMDestMem: 680 return 0; 681 case X86II::MRMSrcMem: 682 // Start from 1, skip any registers encoded in VEX_VVVV or I8IMM, or a 683 // mask register. 684 return 1 + HasVEX_4V + HasMemOp4 + HasEVEX_K; 685 case X86II::MRMXr: 686 case X86II::MRM0r: case X86II::MRM1r: 687 case X86II::MRM2r: case X86II::MRM3r: 688 case X86II::MRM4r: case X86II::MRM5r: 689 case X86II::MRM6r: case X86II::MRM7r: 690 return -1; 691 case X86II::MRMXm: 692 case X86II::MRM0m: case X86II::MRM1m: 693 case X86II::MRM2m: case X86II::MRM3m: 694 case X86II::MRM4m: case X86II::MRM5m: 695 case X86II::MRM6m: case X86II::MRM7m: 696 // Start from 0, skip registers encoded in VEX_VVVV or a mask register. 697 return 0 + HasVEX_4V + HasEVEX_K; 698 case X86II::MRM_C0: case X86II::MRM_C1: case X86II::MRM_C2: 699 case X86II::MRM_C3: case X86II::MRM_C4: case X86II::MRM_C8: 700 case X86II::MRM_C9: case X86II::MRM_CA: case X86II::MRM_CB: 701 case X86II::MRM_CF: case X86II::MRM_D0: case X86II::MRM_D1: 702 case X86II::MRM_D4: case X86II::MRM_D5: case X86II::MRM_D6: 703 case X86II::MRM_D7: case X86II::MRM_D8: case X86II::MRM_D9: 704 case X86II::MRM_DA: case X86II::MRM_DB: case X86II::MRM_DC: 705 case X86II::MRM_DD: case X86II::MRM_DE: case X86II::MRM_DF: 706 case X86II::MRM_E0: case X86II::MRM_E1: case X86II::MRM_E2: 707 case X86II::MRM_E3: case X86II::MRM_E4: case X86II::MRM_E5: 708 case X86II::MRM_E8: case X86II::MRM_E9: case X86II::MRM_EA: 709 case X86II::MRM_EB: case X86II::MRM_EC: case X86II::MRM_ED: 710 case X86II::MRM_EE: case X86II::MRM_F0: case X86II::MRM_F1: 711 case X86II::MRM_F2: case X86II::MRM_F3: case X86II::MRM_F4: 712 case X86II::MRM_F5: case X86II::MRM_F6: case X86II::MRM_F7: 713 case X86II::MRM_F8: case X86II::MRM_F9: case X86II::MRM_FA: 714 case X86II::MRM_FB: case X86II::MRM_FC: case X86II::MRM_FD: 715 case X86II::MRM_FE: case X86II::MRM_FF: 716 return -1; 717 } 718 } 719 720 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or 721 /// higher) register? e.g. r8, xmm8, xmm13, etc. 722 inline bool isX86_64ExtendedReg(unsigned RegNo) { 723 if ((RegNo > X86::XMM7 && RegNo <= X86::XMM15) || 724 (RegNo > X86::XMM23 && RegNo <= X86::XMM31) || 725 (RegNo > X86::YMM7 && RegNo <= X86::YMM15) || 726 (RegNo > X86::YMM23 && RegNo <= X86::YMM31) || 727 (RegNo > X86::ZMM7 && RegNo <= X86::ZMM15) || 728 (RegNo > X86::ZMM23 && RegNo <= X86::ZMM31)) 729 return true; 730 731 switch (RegNo) { 732 default: break; 733 case X86::R8: case X86::R9: case X86::R10: case X86::R11: 734 case X86::R12: case X86::R13: case X86::R14: case X86::R15: 735 case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D: 736 case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D: 737 case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W: 738 case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W: 739 case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B: 740 case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B: 741 case X86::CR8: case X86::CR9: case X86::CR10: case X86::CR11: 742 case X86::CR12: case X86::CR13: case X86::CR14: case X86::CR15: 743 return true; 744 } 745 return false; 746 } 747 748 /// is32ExtendedReg - Is the MemoryOperand a 32 extended (zmm16 or higher) 749 /// registers? e.g. zmm21, etc. 750 static inline bool is32ExtendedReg(unsigned RegNo) { 751 return ((RegNo > X86::XMM15 && RegNo <= X86::XMM31) || 752 (RegNo > X86::YMM15 && RegNo <= X86::YMM31) || 753 (RegNo > X86::ZMM15 && RegNo <= X86::ZMM31)); 754 } 755 756 757 inline bool isX86_64NonExtLowByteReg(unsigned reg) { 758 return (reg == X86::SPL || reg == X86::BPL || 759 reg == X86::SIL || reg == X86::DIL); 760 } 761 } 762 763 } // end namespace llvm; 764 765 #endif 766
