| /external/llvm/lib/Target/R600/ |
| SILowerI1Copies.cpp | 107 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src.getReg());
110 TRI->getCommonSubClass(SrcRC, &AMDGPU::SGPR_64RegClass)) {
137 SrcRC == &AMDGPU::VReg_1RegClass) {
|
| SIFixSGPRCopies.cpp | 191 const TargetRegisterClass *SrcRC;
198 SrcRC = TRI->getSubRegClass(MRI.getRegClass(SrcReg), SrcSubReg);
199 return TRI->isSGPRClass(DstRC) && TRI->hasVGPRs(SrcRC);
|
| SIInstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCVSXCopy.cpp | 99 const TargetRegisterClass *SrcRC =
106 unsigned NewVReg = MRI.createVirtualRegister(SrcRC);
|
| /external/llvm/lib/CodeGen/ |
| PeepholeOptimizer.cpp | 514 const TargetRegisterClass *SrcRC,
517 if (DefRC == SrcRC)
523 return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg,
529 std::swap(DefRC, SrcRC);
534 return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr;
536 return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr;
577 const TargetRegisterClass *SrcRC = MRI->getRegClass(Src);
580 ShouldRewrite = shareSameRegisterFile(*TRI, DefRC, DefSubReg, SrcRC,
[all...] |
| RegisterCoalescer.cpp | 332 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src);
341 NewRC = TRI.getCommonSuperRegClass(SrcRC, SrcSub, DstRC, DstSub,
348 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub);
352 NewRC = TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSub);
355 NewRC = TRI.getCommonSubClass(DstRC, SrcRC);
370 CrossClass = NewRC != DstRC || NewRC != SrcRC;
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXInstrInfo.cpp | 38 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
40 if (DestRC != SrcRC)
|
| /external/llvm/lib/Target/ARM/ |
| ARMBaseRegisterInfo.h | 180 /// \brief SrcRC and DstRC will be morphed into NewRC if this returns true
182 const TargetRegisterClass *SrcRC,
|
| ARMBaseRegisterInfo.cpp | 767 const TargetRegisterClass *SrcRC,
780 if (NewRC->getSize() < 32 && DstRC->getSize() < 32 && SrcRC->getSize() < 32)
786 MRI.getTargetRegisterInfo()->getRegClassWeight(SrcRC);
|
| ARMFastISel.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGFast.cpp | 390 const TargetRegisterClass *SrcRC,
393 CopyFromSU->CopySrcRC = SrcRC;
398 CopyToSU->CopyDstRC = SrcRC;
|
| InstrEmitter.cpp | 156 const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr;
157 SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
171 if (MatchReg && SrcRC->getCopyCost() < 0) {
[all...] |
| ScheduleDAGRRList.cpp | [all...] |
| /external/llvm/include/llvm/Target/ |
| TargetRegisterInfo.h | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | [all...] |
