| /external/clang/test/CodeGen/ |
| ppc64-vector.c | 5 typedef short v4i16 __attribute__((vector_size (8))); typedef
25 v4i16 test_v4i16(v4i16 x)
|
| systemz-abi-vector.c | 16 typedef __attribute__((vector_size(8))) short v4i16; typedef
57 v4i16 pass_v4i16(v4i16 arg) { return arg; }
|
| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 81 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0 },
82 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 0 },
86 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 },
89 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
90 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
118 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
119 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
133 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 },
134 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 },
376 {ISD::VECTOR_SHUFFLE, MVT::v4i16, 2}
[all...] |
| ARMISelLowering.cpp | 432 addDRTypeForNEON(MVT::v4i16);
522 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
524 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
532 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
533 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
534 setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom);
535 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
545 setOperationAction(ISD::CTPOP, MVT::v4i16, Custom);
573 // It is legal to extload from v4i8 to v4i16 or v4i32.
574 for (MVT Ty : {MVT::v8i8, MVT::v4i8, MVT::v2i8, MVT::v4i16, MVT::v2i16
[all...] |
| ARMISelDAGToDAG.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineValueType.h | 75 v4i16 = 28, // 4 x i16 enumerator in enum:llvm::MVT::SimpleValueType
217 return (SimpleTy == MVT::v8i8 || SimpleTy == MVT::v4i16 ||
299 case v4i16:
353 case v4i16:
416 case v4i16:
546 if (NumElements == 4) return MVT::v4i16;
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | 463 case MVT::v4i16:
[all...] |
| AArch64TargetTransformInfo.cpp | 209 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
211 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
238 // Complex, from v4f32: legal type is v4i16, 1 narrowing => ~2
239 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 },
241 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 },
|
| AArch64ISelLowering.cpp | 106 addDRTypeForNEON(MVT::v4i16);
558 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Promote);
559 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Promote);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 555 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
556 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
561 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 },
587 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 6 },
588 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
593 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 4 },
606 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 3 },
610 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 },
619 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
623 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }
[all...] |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/IR/ |
| ValueTypes.cpp | 146 case MVT::v4i16: return "v4i16";
214 case MVT::v4i16: return VectorType::get(Type::getInt16Ty(Context), 4);
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDILISelLowering.cpp | 60 (int)MVT::v4i16,
88 (int)MVT::v4i16,
210 setOperationAction(ISD::UDIV, MVT::v4i16, Expand);
668 } else if (OVT == MVT::v4i16) {
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 170 } else if (LocVT == MVT::v8i8 || LocVT == MVT::v4i16 || LocVT == MVT::v2i32) {
251 } else if (LocVT == MVT::v8i8 || LocVT == MVT::v4i16 || LocVT == MVT::v2i32) {
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.cpp | 88 case MVT::v4i16: return "MVT::v4i16";
|
| /external/llvm/lib/Target/R600/ |
| AMDGPUISelLowering.cpp | 178 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand);
237 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Expand);
238 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Expand);
239 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i16, Expand);
[all...] |
| SIISelLowering.cpp | 117 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Custom);
[all...] |
| R600ISelLowering.cpp | 109 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Expand);
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 66 case MVT::v4i16:
[all...] |
