| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 116 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence
117 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence
137 // Shifts on v4i64/v8i32 on AVX2 is legal even though we declare to
142 { ISD::SHL, MVT::v8i32, 1 },
143 { ISD::SRL, MVT::v8i32, 1 },
144 { ISD::SRA, MVT::v8i32, 1 },
163 { ISD::SDIV, MVT::v8i32, 8*20 },
167 { ISD::UDIV, MVT::v8i32, 8*20 },
293 { ISD::MUL, MVT::v8i32, 4 },
294 { ISD::SUB, MVT::v8i32, 4 }
[all...] |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineValueType.h | 82 v8i32 = 35, // 8 x i32 enumerator in enum:llvm::MVT::SimpleValueType
235 SimpleTy == MVT::v8i32 || SimpleTy == MVT::v4i64);
306 case v8i32:
346 case v8i32:
435 case v8i32:
555 if (NumElements == 8) return MVT::v8i32;
|
| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 91 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
92 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
102 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 },
122 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 },
123 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 },
278 { ISD::SELECT, MVT::v8i1, MVT::v8i32, 4*8 + 1*3 + 1*4 + 1*2 },
|
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86InstComments.cpp | 55 DstVT = MVT::v8i32;
80 DstVT = MVT::v8i32;
220 DecodeBLENDMask(MVT::v8i32,
391 DecodePSHUFMask(MVT::v8i32,
494 DecodeUNPCKHMask(MVT::v8i32, ShuffleMask);
583 DecodeUNPCKLMask(MVT::v8i32, ShuffleMask);
[all...] |
| /external/llvm/lib/IR/ |
| ValueTypes.cpp | 153 case MVT::v8i32: return "v8i32";
221 case MVT::v8i32: return VectorType::get(Type::getInt32Ty(Context), 8);
|
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.cpp | 57 addRegisterClass(MVT::v8i32, &AMDGPU::SReg_256RegClass);
65 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i32, Expand);
84 setOperationAction(ISD::LOAD, MVT::v8i32, Custom);
87 setOperationAction(ISD::STORE, MVT::v8i32, Custom);
160 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Expand);
178 for (MVT VT : {MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32}) {
[all...] |
| AMDGPUISelLowering.cpp | 157 AddPromotedToType(ISD::STORE, MVT::v8f32, MVT::v8i32);
197 AddPromotedToType(ISD::LOAD, MVT::v8f32, MVT::v8i32);
210 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
217 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64TargetTransformInfo.cpp | 360 { ISD::SELECT, MVT::v8i1, MVT::v8i32, 8 * AmortizationCost },
|
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.cpp | 95 case MVT::v8i32: return "MVT::v8i32";
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIISelLowering.cpp | 38 addRegisterClass(MVT::v8i32, &AMDGPU::SReg_256RegClass);
|
