| /external/llvm/lib/CodeGen/ |
| CodeGenPrepare.cpp | 135 /// multiple load/stores of the same address.
624 // %val = load %ptr'
633 // %val = load %ptr'
[all...] |
| /external/llvm/lib/Target/R600/ |
| AMDGPUISelLowering.cpp | 86 // Find a larger type to do a load / store of a vector with.
145 // Lower floating point store/load to integer store/load to reduce the number
187 setOperationAction(ISD::LOAD, MVT::f32, Promote);
188 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
190 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
191 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
193 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
194 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
196 setOperationAction(ISD::LOAD, MVT::v8f32, Promote)
[all...] |
| /external/pdfium/core/src/fxge/win32/ |
| fx_win32_gdipext.cpp | 490 void CGdiplusExt::Load()
[all...] |
| /external/skia/src/utils/ |
| SkLua.cpp | 98 SkLua::Load(fL);
[all...] |
| /external/v8/src/arm64/ |
| macro-assembler-arm64.cc | 588 // Encodable in one load/store instruction.
597 // TODO(all): Should we support register offset for load-store-pair?
606 // Encodable in one load/store pair instruction.
627 void MacroAssembler::Load(const Register& rt,
[all...] |
| /external/valgrind/VEX/priv/ |
| host_ppc_defs.h | 446 Pin_LI, /* load word (32/64-bit) immediate (fake insn) */
459 Pin_Load, /* zero-extending load a 8|16|32|64 bit value from mem */
460 Pin_LoadL, /* load-linked (lwarx/ldarx) 32|64 bit value from mem */
470 Pin_FpLdSt, /* FP load/store */
480 Pin_AvLdSt, /* AV load/store (kludging for AMode_IR) */
655 } Load;
656 /* Load-and-reserve (lwarx, ldarx) */
741 /* Load FP Status & Control Register */
850 /* Load AltiVec Status & Control Register */
[all...] |
| ir_opt.c | 80 Immediately prior to any load or store, those parts of the guest
84 be up-to-date at the point of the load/store.
277 return isIRAtom(e->Iex.Load.addr);
349 IRExpr_Load(ex->Iex.Load.end,
350 ex->Iex.Load.ty,
351 flatten_Expr(bb, ex->Iex.Load.addr))));
[all...] |
| /external/llvm/tools/llvm-objdump/ |
| MachODump.cpp | 383 MachOObjectFile::LoadCommandInfo Load = O->getFirstLoadCommandInfo();
385 if (Load.C.cmd == MachO::LC_SEGMENT_64) {
386 MachO::segment_command_64 Seg = O->getSegment64LoadCommand(Load);
388 MachO::section_64 Sec = O->getSection64(Load, J);
413 } else if (Load.C.cmd == MachO::LC_SEGMENT) {
414 MachO::segment_command Seg = O->getSegmentLoadCommand(Load);
416 MachO::section Sec = O->getSection(Load, J);
445 Load = O->getNextLoadCommandInfo(Load);
550 MachOObjectFile::LoadCommandInfo Load = O->getFirstLoadCommandInfo()
[all...] |
| /external/clang/lib/Sema/ |
| SemaChecking.cpp | 605 /// the pointer arguments for Neon load/store intrinsics.
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| DAGCombiner.cpp | 48 STATISTIC(OpsNarrowed , "Number of load/op/store narrowed");
49 STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int");
50 STATISTIC(SlicedLoads, "Number of load sliced");
72 /// Hidden option to stress test load slicing, i.e., when this option
73 /// is enabled, load slicing bypasses most of its profitability guards.
75 StressLoadSlicing("combiner-stress-load-slicing", cl::Hidden,
76 cl::desc("Bypass the profitability model of load "
81 MaySplitLoadIndex("combiner-split-load-index", cl::Hidden, cl::init(true),
117 // AA - Used for DAG load/store alias analysis.
192 /// \brief Replace an ISD::EXTRACT_VECTOR_ELT of a load with a narrowe
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 50 Align(cl::desc("Load/store alignment support"),
428 // load, floating-point truncating stores, or v2i32->v2i16 truncating store.
623 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
624 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i32);
629 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
630 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i64);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 96 setOperationAction(ISD::LOAD, VT, Promote);
97 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT);
571 setTargetDAGCombine(ISD::LOAD);
641 // ARM does not have i1 sign extending load.
645 // ARM supports all 4 flavors of integer indexed load / store.
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 49 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
55 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
85 // PowerPC has pre-inc load and store's.
116 // PowerPC does not support direct load / store of condition registers
117 setOperationAction(ISD::LOAD, MVT::i1, Custom);
252 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
429 setOperationAction(ISD::LOAD , VT, Promote);
430 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
493 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
572 setOperationAction(ISD::LOAD, MVT::v2f64, Legal)
[all...] |
| /prebuilts/gcc/linux-x86/host/x86_64-w64-mingw32-4.8/x86_64-w64-mingw32/include/ |
| agtctl.h | [all...] |
| agtsvr.h | [all...] |
| cdosys.h | [all...] |
| mmcobj.h | 356 virtual HRESULT WINAPI Load(BSTR Filename) = 0;
379 HRESULT (WINAPI *Load)(_Application *This,BSTR Filename);
404 #define _Application_Load(This,Filename) (This)->lpVtbl->Load(This,Filename)
[all...] |
| ocidl.h | [all...] |
| urlmon.h | 396 virtual HRESULT WINAPI Load(WINBOOL fFullyAvailable,IMoniker *pimkName,LPBC pibc,DWORD grfMode) = 0;
409 HRESULT (WINAPI *Load)(IPersistMoniker *This,WINBOOL fFullyAvailable,IMoniker *pimkName,LPBC pibc,DWORD grfMode);
424 #define IPersistMoniker_Load(This,fFullyAvailable,pimkName,pibc,grfMode) (This)->lpVtbl->Load(This,fFullyAvailable,pimkName,pibc,grfMode)
[all...] |
| cdoex.h | [all...] |
| objidl.h | [all...] |
| strmif.h | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 681 setOperationAction(ISD::LOAD, VT, Expand);
[all...] |
| /external/valgrind/VEX/pub/ |
| libvex_ir.h | 74 eg. (3 + (4 * load(addr1)).
253 /* IREndness is used in load IRExprs and store IRStmts. */
[all...] |
| /prebuilts/misc/common/jython/ |
| jython.jar | |
