| /external/vixl/test/ |
| test-disasm-a64.cc | 748 COMPARE(ands(w23, w24, Operand(0x0000000f)), "ands w23, w24, #0xf");
749 COMPARE(ands(x25, x26, Operand(0x800000000000000f)),
750 "ands x25, x26, #0x800000000000000f");
765 COMPARE(bics(w27, w28, Operand(0xfffffff7)), "ands w27, w28, #0x8");
767 "ands x29, x0, #0x100000000");
771 COMPARE(ands(xzr, xzr, Operand(7)), "tst xzr, #0x7");
[all...] |
| test-assembler-a64.cc | 742 TEST(ands) {
747 __ Ands(w0, w1, Operand(w1));
758 __ Ands(w0, w0, Operand(w1, LSR, 4));
769 __ Ands(x0, x0, Operand(x1, ROR, 1));
779 __ Ands(w0, w0, Operand(0xf));
789 __ Ands(w0, w0, Operand(0x80000000));
[all...] |
| /external/guava/guava-tests/test/com/google/common/base/ |
| PredicatesTest.java | 910 // While not a contractual requirement, we'd like the hash codes for ands
[all...] |
| /external/libavc/common/armv8/ |
| ih264_intra_pred_chroma_av8.s | 118 ands x6, x4, x19
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrInfo.td | [all...] |
| /external/v8/src/arm64/ |
| assembler-arm64.cc | 1185 void Assembler::ands(const Register& rd, function in class:v8::internal::Assembler
[all...] |
| /libcore/luni/src/main/java/java/util/ |
| BitSet.java | 461 * Logically ands the bits of this {@code BitSet} with {@code bs}.
|
| /external/llvm/test/MC/AArch64/ |
| arm64-aliases.s | 43 ands wzr, w1, w2, lsl #2
44 ands xzr, x1, x2, lsl #3
|
| basic-a64-diagnostics.s | [all...] |
| /external/pcre/dist/sljit/ |
| sljitNativeARM_T2_32.c | 100 #define ANDS 0x4000
757 return push_inst16(compiler, ANDS | RD3(dst) | RN3(arg2));
[all...] |
| /frameworks/rs/cpu_ref/ |
| rsCpuIntrinsics_advsimd_ColorMatrix.S | [all...] |
| rsCpuIntrinsics_advsimd_Blur.S | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| README.txt | 336 We could collapse a bunch of those ORs and ANDs and generate the following
|
| /external/valgrind/none/tests/arm64/ |
| integer.c | 491 TESTINST2("ands x3,x4, #0x8080808080808080", 0x843fdf810277796e, x3, x4, 0);
492 TESTINST2("ands x3,x4, #0xC0C0C0C0C0C0C0C0", 0xc5446fe48c610b28, x3, x4, 0);
493 TESTINST2("ands x3,x4, #0x8080808080808080", 0x143fdf810277796e, x3, x4, 0);
494 TESTINST2("ands x3,x4, #0xC0C0C0C0C0C0C0C0", 0xA5446fe48c610b28, x3, x4, 0);
495 TESTINST2("ands x3,x4, #0x8080808080808080", 0x7070707070707070, x3, x4, 0);
496 TESTINST2("ands x3,x4, #0x8080808080808080", 0xF070707070707070, x3, x4, 0);
501 TESTINST2("ands w3,w4, #0x80808080", 0x843fdf810277796e, x3, x4, 0);
502 TESTINST2("ands w3,w4, #0xC0C0C0C0", 0xc5446fe48c610b28, x3, x4, 0);
503 TESTINST2("ands w3,w4, #0x80808080", 0x143fdf810277796e, x3, x4, 0);
504 TESTINST2("ands w3,w4, #0xC0C0C0C0", 0xA5446fe48c610b28, x3, x4, 0)
[all...] |
| /external/boringssl/src/crypto/chacha/ |
| chacha_vec_arm.S | 914 ands r9, r3, #63
|
| /external/boringssl/src/include/openssl/ |
| bio.h | 203 /* BIO_clear_flags ANDs |bio->flags| with the bitwise-complement of |flags|. */
[all...] |
| /external/vixl/src/vixl/a64/ |
| assembler-a64.cc | 963 void Assembler::ands(const Register& rd, function in class:vixl::Assembler
966 Logical(rd, rn, operand, ANDS);
972 ands(AppropriateZeroRegFor(rn), rn, operand);
[all...] |
| disasm-a64.cc | 257 mnemonic = "ands";
318 mnemonic = "ands";
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.cpp | 481 // cmp reg, #foo is actually ands xzr, reg, #1<<foo.
686 // ANDS does not use the same encoding scheme as the others xxxS
[all...] |
| AArch64ISelLowering.cpp | [all...] |
| /external/llvm/test/MC/ARM/ |
| basic-thumb2-instructions.s | 155 ands r3, r12, #0xf
159 ands r1, r9, #0xffffffff
162 @ CHECK: ands r3, r12, #15 @ encoding: [0x1c,0xf0,0x0f,0x03]
166 @ CHECK: ands r1, r9, #4294967295 @ encoding: [0x19,0xf0,0xff,0x31]
173 ands r2, r1, r7, lsl #1
174 ands.w r4, r5, r2, lsr #20
179 @ CHECK: ands.w r2, r1, r7, lsl #1 @ encoding: [0x11,0xea,0x47,0x02]
180 @ CHECK: ands.w r4, r5, r2, lsr #20 @ encoding: [0x15,0xea,0x12,0x54]
[all...] |
| /external/vixl/doc/ |
| supported-instructions.md | 85 ### ANDS ###
89 void ands(const Register& rd,
[all...] |
| /external/libavc/encoder/arm/ |
| ime_distortion_metrics_a9q.s | 1024 ands r11, r8, #1 @II See if we are at even or odd block
[all...] |
| /external/skia/src/opts/ |
| SkBlitRow_opts_arm_neon.cpp | 200 "ands ip, %[count], #7 \n\t"
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineAndOrXor.cpp | 614 // Look for ANDs in the LHS icmp.
670 // Look for ANDs in on the right side of the RHS icmp.
[all...] |
