| /system/core/libcutils/arch-arm64/ |
| android_memset.S | 68 ands A_lw, A_lw, #0xffff
86 ands tmp1, count, #0x30
123 ands tmp2, tmp2, #15
156 ands tmp2, tmp2, #15
181 ands tmp2, tmp2, zva_bits_x
208 ands count, count, zva_bits_x
|
| /external/libvpx/libvpx/vp8/common/arm/armv6/ |
| copymem8x4_v6.asm | 29 ands r4, r0, #7
32 ands r4, r0, #3
|
| copymem8x8_v6.asm | 29 ands r4, r0, #7
32 ands r4, r0, #3
|
| /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp8/common/arm/armv6/ |
| copymem8x4_v6.asm | 29 ands r4, r0, #7
32 ands r4, r0, #3
|
| copymem8x8_v6.asm | 29 ands r4, r0, #7
32 ands r4, r0, #3
|
| /bionic/libc/arch-arm/cortex-a9/bionic/ |
| __strcat_chk.S | 63 ands r3, r0, #7
74 ands ip, ip, #0x80808080
79 ands ip, ip, #0x80808080
155 ands ip, ip, #0x80808080
|
| __strcpy_chk.S | 49 ands r3, r0, #7
60 ands ip, ip, #0x80808080
65 ands ip, ip, #0x80808080
141 ands ip, ip, #0x80808080
|
| strlen.S | 67 ands r3, r0, #7
78 ands ip, ip, #0x80808080
83 ands ip, ip, #0x80808080
159 ands ip, ip, #0x80808080
|
| memcpy_base.S | 46 ands r3, r3, #0x3
55 ands r3, r3, #0xF
157 ands r3, #3
|
| /external/llvm/test/CodeGen/PowerPC/ |
| rlwinm2.ll | 1 ; All of these ands and shifts should be folded into rlw[i]nm instructions
|
| /external/llvm/test/CodeGen/SystemZ/ |
| atomicrmw-and-01.ll | 1 ; Test 8-bit atomic ANDs.
78 ; Check ANDs of -2 (-1 isn't useful). We AND the rotated word with 0xfeffffff.
92 ; Check ANDs of 1. We AND the rotated word with 0x01ffffff.
120 ; Check ANDs of a large unsigned value. We AND the rotated word with
|
| atomicrmw-and-02.ll | 1 ; Test 16-bit atomic ANDs.
78 ; Check ANDs of -2 (-1 isn't useful). We AND the rotated word with 0xfffeffff.
92 ; Check ANDs of 1. We AND the rotated word with 0x0001ffff.
120 ; Check ANDs of a large unsigned value. We AND the rotated word with
|
| risbg-02.ll | 5 ; Test a case with two ANDs.
27 ; Test a case with two ANDs and a shift.
|
| and-02.ll | 1 ; Test 32-bit ANDs in which the second operand is constant.
5 ; ANDs with 1 can use NILF.
32 ; ANDs with 5 must use NILF.
86 ; ANDs of 0xffff are zero extensions from i16.
|
| atomicrmw-and-04.ll | 1 ; Test 64-bit atomic ANDs.
5 ; Check ANDs of a variable.
19 ; Check ANDs of 1, which are done using a register. (We could use RISBG
|
| /bionic/libc/arch-arm/generic/bionic/ |
| memset.S | 71 ands r3, r3, #3
97 ands r3, r3, #0x1C
|
| strcmp.S | 62 ands r2, r0, #3
181 ands r3, r3, b1, lsl #7
229 ands r3, r3, b1, lsl #7
274 ands r3, r3, b1, lsl #7
|
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-ands-bad-peephole.ll | 2 ; Check that ANDS (tst) is not merged with ADD when the immediate
|
| /external/llvm/test/CodeGen/Thumb2/ |
| thumb2-and.ll | 5 ; CHECK: ands r0, r1
|
| /bionic/libc/arch-arm64/denver64/bionic/ |
| memcpy_base.S | 72 ands tmp1, count, #0x30
89 ands count, count, #15
124 ands tmp2, tmp2, #15 /* Bytes to reach alignment. */
|
| /bionic/libc/arch-arm64/generic/bionic/ |
| memcpy_base.S | 66 ands tmp1, count, #0x30
83 ands count, count, #15
118 ands tmp2, tmp2, #15 /* Bytes to reach alignment. */
|
| memmove.S | 93 ands tmp1, count, #0x30
133 ands tmp2, src, #15 /* Bytes to reach alignment. */
220 ands tmp1, count, #0x30
261 ands tmp2, tmp2, #15 /* Bytes to reach alignment. */
|
| /external/valgrind/none/tests/arm/ |
| v6intThumb.c | [all...] |
| /external/llvm/test/MC/ARM/ |
| thumb2-narrow-dp.ll | 15 ANDS r0, r2, r1 // Must be wide - 3 distinct registers
16 ANDS r2, r2, r1 // Should choose narrow
17 ANDS r2, r1, r2 // Should choose narrow - commutative
18 ANDS.W r0, r0, r1 // Explicitly wide
19 ANDS.W r3, r1, r3
21 ANDS r7, r7, r1 // Should use narrow
22 ANDS r7, r1, r7 // Commutative
23 ANDS r8, r1, r8 // high registers so must use wide encoding
24 ANDS r8, r8, r1
25 ANDS r0, r8, r
[all...] |
| /bionic/libc/arch-arm/cortex-a15/bionic/ |
| memcpy_base.S | 87 ands r3, r3, #0xF
169 ands r3, r3, #0x3
195 ands ip, r0, #3
211 ands r3, r0, #4
|
