| /external/llvm/lib/Target/Mips/ |
| MipsSEFrameLowering.cpp | 271 // spill + reload via ldc1
276 // The FP64A ABI (fp64 with nooddspreg) must also use a spill/reload sequence
280 // allocation so for now we use a spill/reload sequence for all
298 // We re-use the same spill slot each time so that the stack frame doesn't
323 // spill + reload via ldc1
328 // The FP64A ABI (fp64 with nooddspreg) must also use a spill/reload sequence
332 // allocation so for now we use a spill/reload sequence for all
352 // We re-use the same spill slot each time so that the stack frame doesn't
479 // Insert instructions that spill eh data registers.
580 // It's killed at the spill, unless the register is RA and return addres
[all...] |
| /external/llvm/lib/CodeGen/ |
| RegisterScavenging.cpp | 13 // spill slots.
383 // have to spill.
393 // If we found an unused register there is no reason to spill it.
406 // We need to scavenge a register but have no spill slot, the target
415 // otherwise, use the emergency stack spill slot.
417 // Spill the scavenged register before I.
419 "Cannot scavenge register without an emergency spill slot!");
441 DEBUG(dbgs() << "Scavenged register (with spill): " << TRI->getName(SReg) <<
|
| /external/llvm/test/CodeGen/Mips/ |
| stldst.ll | 36 ; 16: sw ${{[0-9]+}}, {{[0-9]+}} ( $sp ); # 4-byte Folded Spill
38 ; 16: sw ${{[0-9]+}}, {{[0-9]+}} ( $sp ); # 4-byte Folded Spill
|
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_fs_reg_allocate.cpp | 233 /* Failed to allocate registers. Spill a reg, and the caller will
239 fail("no register to spill\n");
291 * spill. Nothing else will make it up to MRF 14/15.
311 * spill/unspill we'll have to do, and guess that the insides of
322 * registers have a width of 1 so if we try to spill them we'll
383 /* Generate spill/unspill instructions for the objects being
384 * spilled. Right now, we spill or unspill the whole thing to a
386 * could just spill/unspill the GRF being accessed.
|
| brw_wm_pass2.c | 166 /* Allocate a spill slot. Note that allocations start from 0x40 -
174 /* The spill will be done in brw_wm_emit.c immediately after the
188 * TODO: implement spill-to-reg so that we can rearrange discontigous
189 * free regs and then spill the oldest non-free regs in sequence.
303 * result registers. Where necessary spill registers to scratch space
|
| /external/v8/test/mjsunit/regress/ |
| regress-crbug-173907.js | 36 function spill() { function
45 spill(); // At this point initial values for phi1 and phi2 are spilled.
|
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-2011-03-09-CPSRSpill.ll | 3 ; Can't copy or spill / restore CPSR.
|
| /external/llvm/test/CodeGen/ARM/ |
| gpr-paired-spill-thumbinst.ll | 17 ; Make sure we are actually creating the Thumb versions of the spill
|
| /external/llvm/test/CodeGen/Hexagon/ |
| validate-offset.ll | 5 ; by 'Hexagon Expand Predicate Spill Code' pass.
|
| /external/llvm/test/CodeGen/PowerPC/ |
| buildvec_canonicalize.ll | 12 ; The fmul will spill a vspltisw to create a -0.0 vector used as the addend
|
| frame-size.ll | 10 ; Check that the RS spill slot has been allocated (because the estimate
|
| vrspill.ll | 5 ; This verifies that we generate correct spill/reload code for vector regs.
|
| /external/llvm/test/CodeGen/Thumb/ |
| 2011-06-16-NoGPRs.ll | 6 ; to spill them.
|
| /external/llvm/test/CodeGen/Thumb2/ |
| inflate-regs.ll | 7 ; RAGreedy should split the range and use d16-d31 to avoid a spill.
|
| /external/llvm/test/CodeGen/X86/ |
| 2008-01-08-SchedulerCrash.ll | 3 ; Test scheduling a multi-use compare. We should neither spill flags
|
| licm-regpressure.ll | 7 ; CHECK-NOT: Spill
|
| statepoint-allocas.ll | 3 ; exact meaning is up to the consumer of the stackmap) and as an explicit spill
86 ; Direct Spill Slot [RSP+0]
110 ; Direct Spill Slot [RSP+0]
|
| /external/v8/src/ |
| hydrogen-environment-liveness.h | 18 // unnecessary spill slot moves. Therefore it is beneficial to trim the
|
| /frameworks/support/v7/mediarouter/res/values-nb/ |
| strings.xml | 27 <string name="mr_media_route_controller_play" msgid="5214423499524760404">"Spill av"</string>
|
| /prebuilts/sdk/current/support/v7/mediarouter/res/values-nb/ |
| strings.xml | 27 <string name="mr_media_route_controller_play" msgid="5214423499524760404">"Spill av"</string>
|
| /art/compiler/jni/quick/mips/ |
| calling_convention_mips.cc | 90 // We spill the argument registers on MIPS to free them up for scratch use, we then assume
138 // Compute spill mask to agree with callee saves initialized in the constructor
155 // Plus return value spill area size
|
| /art/compiler/jni/quick/mips64/ |
| calling_convention_mips64.cc | 94 // We spill the argument registers on MIPS64 to free them up for scratch use,
140 // Compute spill mask to agree with callee saves initialized in the constructor
156 // Plus return value spill area size
|
| /external/llvm/lib/Target/R600/ |
| SIRegisterInfo.cpp | 43 // Reserve some VGPRs to use as temp registers in case we have to spill VGPRs
133 default: llvm_unreachable("Invalid spill opcode");
207 // SGPR register spill
218 struct SIMachineFunctionInfo::SpilledReg Spill =
221 if (Spill.VGPR == AMDGPU::NoRegister) {
228 Spill.VGPR)
230 .addImm(Spill.Lane);
249 struct SIMachineFunctionInfo::SpilledReg Spill =
252 if (Spill.VGPR == AMDGPU::NoRegister) {
263 .addReg(Spill.VGPR
[all...] |
| /external/llvm/test/MC/Mips/ |
| elf-tls.s | 34 sw $ra, 20($sp) # 4-byte Folded Spill
66 sw $ra, 20($sp) # 4-byte Folded Spill
98 sw $ra, 20($sp) # 4-byte Folded Spill
|
| /external/llvm/include/llvm/Target/ |
| TargetFrameLowering.h | 32 /// spill locations) can be stored.
96 /// assignCalleeSavedSpillSlots - Allows target to override spill slot
99 /// returns false, spill slots will be assigned using generic implementation.
116 /// allowed to spill it anywhere it chooses.
149 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee
|
