| /external/mesa3d/src/mesa/drivers/dri/r200/ |
| r200_sanity.c | [all...] |
| /external/skia/src/core/ |
| SkBitmapProcState.cpp | [all...] |
| /external/valgrind/VEX/priv/ |
| host_ppc_defs.h | 869 HReg src2; member in struct:__anon19706::__anon19707::__anon19757
[all...] |
| /frameworks/rs/cpu_ref/ |
| rsCpuIntrinsics_neon_Resize.S | 171 * uint8_t const * restrict src2, // [sp,#12] -> [sp,#116] -> r7
201 ldrd r6,r7, [lr,#112] // src1, src2
|
| /external/llvm/lib/Target/ARM/ |
| ARMInstrVFP.td | 874 (outs GPR:$Rt, GPR:$Rt2), (ins SPR:$src1, SPR:$src2),
875 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $src1, $src2",
[all...] |
| ARMInstrThumb2.td | [all...] |
| /external/protobuf/gtest/test/ |
| gtest_unittest.cc | 861 const std::string src2("Hi");
862 const String dest2 = src2;
882 const String src2("Hi");
883 const std::string dest2 = src2;
902 const ::string src2("Hi");
903 const String dest2 = src2;
923 const String src2("Hi");
924 const ::string dest2 = src2;
[all...] |
| /external/v8/src/mips/ |
| macro-assembler-mips.cc | 80 Register src1, const Operand& src2) {
81 Branch(2, NegateCondition(cond), src1, src2);
95 Register src1, const Operand& src2) {
96 Branch(2, NegateCondition(cond), src1, src2);
[all...] |
| /external/v8/src/mips64/ |
| macro-assembler-mips64.cc | 83 Register src1, const Operand& src2) {
84 Branch(2, NegateCondition(cond), src1, src2);
98 Register src1, const Operand& src2) {
99 Branch(2, NegateCondition(cond), src1, src2);
[all...] |
| /art/compiler/dex/quick/ |
| mir_to_lir.h | 186 int32_t operands[5]; // [0..4] = [dest, src1, src2, extra, extra2].
659 LIR* NewLIR3(int opcode, int dest, int src1, int src2);
660 LIR* NewLIR4(int opcode, int dest, int src1, int src2, int info);
661 LIR* NewLIR5(int opcode, int dest, int src1, int src2, int info1, int info2);
[all...] |
| /external/mesa3d/src/mesa/program/ |
| ir_to_mesa.cpp | 293 src_reg src0, src_reg src1, src_reg src2);
351 src_reg src0, src_reg src1, src_reg src2)
363 num_reladdr += src2.reladdr != NULL;
365 reladdr_to_temp(ir, &src2, &num_reladdr);
379 inst->src[2] = src2;
[all...] |
| /external/libhevc/common/x86/ |
| ihevc_weighted_pred_sse42_intr.c | [all...] |
| /external/vixl/src/vixl/a64/ |
| simulator-a64.cc | 279 int64_t src2,
286 int64_t signed_sum = src1 + src2 + carry_in;
292 u2 = static_cast<uint64_t>(src2) & kWRegMask;
301 int64_t s_src2 = src2 << (kXRegSize - kWRegSize);
307 u2 = static_cast<uint64_t>(src2);
315 V = ((src1 ^ src2) >= 0) && ((src1 ^ result) < 0);
[all...] |
| /bootable/recovery/updater/ |
| install.c | 612 // symlink target src1 src2 ...
613 // unlinks any previously existing src1, src2, etc before creating symlinks.
[all...] |
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86InstComments.cpp | [all...] |
| /external/opencv/cv/src/ |
| cvlkpyramid.cpp | 238 const float* src2 = src + src_step; local
243 float t0 = (src3[x] + src[x])*smooth_k[0] + src2[x]*smooth_k[1];
[all...] |
| /external/v8/src/arm64/ |
| macro-assembler-arm64-inl.h | [all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXIntrinsics.td | 138 (ins s0_regclass:$src0, s1_regclass:$src1, s2_regclass:$src2),
141 (IntOP s0_regclass:$src0, s1_regclass:$src1, s2_regclass:$src2))]>;
157 def INT_NVVM_PRMT : F_MATH_3<"prmt.b32 \t$dst, $src0, $src1, $src2;", Int32Regs,
293 def INT_NVVM_SAD_I : F_MATH_3<"sad.s32 \t$dst, $src0, $src1, $src2;",
295 def INT_NVVM_SAD_UI : F_MATH_3<"sad.u32 \t$dst, $src0, $src1, $src2;",
403 : F_MATH_3<"fma.rn.ftz.f32 \t$dst, $src0, $src1, $src2;", Float32Regs,
405 def INT_NVVM_FMA_RN_F : F_MATH_3<"fma.rn.f32 \t$dst, $src0, $src1, $src2;",
408 : F_MATH_3<"fma.rz.ftz.f32 \t$dst, $src0, $src1, $src2;", Float32Regs,
410 def INT_NVVM_FMA_RZ_F : F_MATH_3<"fma.rz.f32 \t$dst, $src0, $src1, $src2;",
413 : F_MATH_3<"fma.rm.ftz.f32 \t$dst, $src0, $src1, $src2;", Float32Regs
[all...] |
| /art/compiler/dex/ |
| type_inference_test.cc | 139 #define DEF_PHI2(bb, reg, src1, src2) \
140 { bb, static_cast<Instruction::Code>(kMirOpPhi), 0, 0u, 2u, { src1, src2 }, 1, { reg } }
141 #define DEF_BINOP(bb, opcode, result, src1, src2) \
142 { bb, opcode, 0u, 0u, 2, { src1, src2 }, 1, { result } }
[all...] |
| /external/icu/icu4j/main/classes/collate/src/com/ibm/icu/text/ |
| CollationKey.java | 549 // copy level from src2 not including 00 or 01
|
| /external/libhevc/common/arm/ |
| ihevc_weighted_pred_bi_default.s | 48 @* dst = ( (src1 + lvl_shift1) + (src2 + lvl_shift2) + 1 << (shift - 1) )
|
| /external/libhevc/common/arm64/ |
| ihevc_weighted_pred_bi_default.s | 48 //* dst = ( (src1 + lvl_shift1) + (src2 + lvl_shift2) + 1 << (shift - 1) )
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrInfo.td | [all...] |
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_eu.h | 846 struct brw_reg src2);
|
| brw_optimize.c | 654 * DP4 dst.x src1 src2
|
