| /external/llvm/lib/Target/PowerPC/ |
| PPCFrameLowering.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.cpp | 377 const TargetRegisterClass *RC =
497 const TargetRegisterClass *RC = nullptr;
717 const TargetRegisterClass *OpRegCstraints =
[all...] |
| /external/llvm/lib/CodeGen/ |
| RegAllocGreedy.cpp | 541 const TargetRegisterClass &RC = *MRI->getRegClass(Reg);
842 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg.reg);
[all...] |
| MachineLICM.cpp | [all...] |
| MachineFunction.cpp | 436 const TargetRegisterClass *RC) {
440 const TargetRegisterClass *VRegRC = MRI.getRegClass(VReg);
[all...] |
| RegAllocPBQP.cpp | 568 const TargetRegisterClass *TRC = MRI.getRegClass(VReg);
707 const TargetRegisterClass &RC = *MRI.getRegClass(LI.reg);
|
| TailDuplication.cpp | 405 const TargetRegisterClass *RC = MRI->getRegClass(DefReg);
442 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
[all...] |
| TwoAddressInstructionPass.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGRRList.cpp | 231 const TargetRegisterClass*,
232 const TargetRegisterClass*,
291 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(Reg);
300 const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
308 const TargetRegisterClass *RC = TII->getRegClass(Desc, Idx, TRI, MF);
[all...] |
| TargetLowering.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | [all...] |
| MipsSEISelLowering.cpp | 236 const TargetRegisterClass *
246 addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
295 addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
[all...] |
| MipsSEISelDAGToDAG.cpp | 136 const TargetRegisterClass *RC;
926 const TargetRegisterClass *RC = TLI->getRegClassFor(ResVecTySimple);
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonExpandCondsets.cpp | 647 const TargetRegisterClass *VC = MRI->getRegClass(RS.Reg);
655 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(PhysS);
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrInfo.cpp | 593 const TargetRegisterClass *RC,
609 const TargetRegisterClass *RC,
[all...] |
| SystemZISelLowering.cpp | 508 static std::pair<unsigned, const TargetRegisterClass *>
510 const TargetRegisterClass *RC, const unsigned *Map) {
521 std::pair<unsigned, const TargetRegisterClass *>
717 const TargetRegisterClass *RC;
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXAsmPrinter.cpp | 300 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
563 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
[all...] |
| NVPTXISelLowering.h | 472 std::pair<unsigned, const TargetRegisterClass *>
|
| /external/llvm/lib/Target/R600/ |
| AMDGPUISelDAGToDAG.cpp | 82 const TargetRegisterClass *getOperandRegClass(SDNode *N, unsigned OpNo) const;
161 const TargetRegisterClass *AMDGPUDAGToDAGISel::getOperandRegClass(SDNode *N,
181 const TargetRegisterClass *SuperRC =
286 const TargetRegisterClass *RC = getOperandRegClass(*U, U.getOperandNo());
[all...] |
| R600MachineScheduler.cpp | 214 const TargetRegisterClass *RC) const {
|
| SILoadStoreOptimizer.cpp | 246 const TargetRegisterClass *SuperRC
|
| SIISelLowering.cpp | 553 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDGPUISelLowering.cpp | 314 const TargetRegisterClass *RC,
|
| /external/llvm/lib/Target/ARM/ |
| Thumb2InstrInfo.cpp | 127 const TargetRegisterClass *RC,
170 const TargetRegisterClass *RC,
|
| /external/llvm/include/llvm/CodeGen/ |
| MachineBasicBlock.h | 325 unsigned addLiveIn(unsigned PhysReg, const TargetRegisterClass *RC);
|
