| /external/llvm/test/MC/AArch64/ |
| optional-hash.s | 14 // CHECK: fcmeq v0.2s, v31.2s, #0.0
15 fcmeq v0.2s, v31.2s, 0.0
|
| neon-scalar-fp-compare.s | 9 fcmeq s10, s11, s12
10 fcmeq d20, d21, d22
12 // CHECK: fcmeq s10, s11, s12 // encoding: [0x6a,0xe5,0x2c,0x5e]
13 // CHECK: fcmeq d20, d21, d22 // encoding: [0xb4,0xe6,0x76,0x5e]
19 fcmeq s10, s11, #0.0
20 fcmeq d20, d21, #0.0
21 fcmeq s10, s11, #0
22 fcmeq d20, d21, #0x0
24 // CHECK: fcmeq s10, s11, #0.0 // encoding: [0x6a,0xd9,0xa0,0x5e]
25 // CHECK: fcmeq d20, d21, #0.0 // encoding: [0xb4,0xda,0xe0,0x5e
[all...] |
| neon-compare-instructions.s | 197 fcmeq v0.2s, v31.2s, v16.2s
198 fcmeq v4.4s, v7.4s, v15.4s
199 fcmeq v29.2d, v2.2d, v5.2d
201 // CHECK: fcmeq v0.2s, v31.2s, v16.2s // encoding: [0xe0,0xe7,0x30,0x0e]
202 // CHECK: fcmeq v4.4s, v7.4s, v15.4s // encoding: [0xe4,0xe4,0x2f,0x4e]
203 // CHECK: fcmeq v29.2d, v2.2d, v5.2d // encoding: [0x5d,0xe4,0x65,0x4e]
346 fcmeq v0.2s, v31.2s, #0.0
347 fcmeq v4.4s, v7.4s, #0.0
348 fcmeq v29.2d, v2.2d, #0.0
349 fcmeq v0.2s, v31.2s, #
[all...] |
| neon-diagnostics.s | 541 fcmeq v0.2d, v1.2s, v2.2d
542 fcmeq v0.16b, v1.16b, v2.16b
543 fcmeq v0.8b, v1.4h, v2.4h
546 // CHECK-ERROR: fcmeq v0.2d, v1.2s, v2.2d
549 // CHECK-ERROR: fcmeq v0.16b, v1.16b, v2.16b
552 // CHECK-ERROR: fcmeq v0.8b, v1.4h, v2.4h
673 fcmeq v0.2d, v1.2s, #0.0
674 fcmeq v0.16b, v1.16b, #0.0
675 fcmeq v0.8b, v1.4h, #1.0
676 fcmeq v0.8b, v1.4h, #
[all...] |
| arm64-advsimd.s | 313 fcmeq.2s v0, v0, v0
383 ; CHECK: fcmeq.2s v0, v0, v0 ; encoding: [0x00,0xe4,0x20,0x0e]
592 fcmeq.2s v0, v0, #0
611 ; CHECK: fcmeq.2s v0, v0, #0.0 ; encoding: [0x00,0xd8,0xa0,0x0e]
[all...] |
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-setcc-int-to-fp-combine.ll | 5 ; CHECK-NEXT: fcmeq.4s v0, v0, v1
40 ; CHECK-NEXT: fcmeq.4s v0, v0, v1
|
| arm64-neon-select_cc.ll | 17 ; CHECK: fcmeq [[MASK:v[0-9]+]].2s, v0.2s, v1.2s
27 ; CHECK: fcmeq d[[MASK:[0-9]+]], d0, d1
48 ; CHECK: fcmeq [[MASK:v[0-9]+]].4s, v0.4s, v1.4s
58 ; CHECK: fcmeq [[MASK:v[0-9]+]].2d, v0.2d, v1.2d
139 ; CHECK: fcmeq [[MASK:v[0-9]+]].2s, v0.2s, v1.2s
148 ; CHECK: fcmeq [[MASK:v[0-9]+]].2s, v0.2s, v1.2s
158 ; CHECK: fcmeq [[MASK:v[0-9]+]].4s, v0.4s, v1.4s
180 ; CHECK: fcmeq d[[MASK:[0-9]+]], d0, d1
200 ; CHECK: fcmeq [[MASK:v[0-9]+]].2d, v0.2d, v1.2d
|
| aarch64-neon-v1i1-setcc.ll | 41 ; CHECK: fcmeq d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
|
| arm64-neon-v1i1-setcc.ll | 37 ; CHECK: fcmeq d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
|
| neon-compare-instructions.ll | [all...] |
| arm64-vcmp.ll | 191 ; CHECK: fcmeq {{d[0-9]+}}, d0, d1
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.h | 128 FCMEQ,
|
| AArch64SchedA57.td | 432 def : InstRW<[A57Write_5cyc_1V], (instregex "^(FACGE|FACGT|FCMEQ|FCMGE|FCMGT|FCMLE|FCMLT)(v2f32|32|64|v1i32|v2i32|v1i64)")>;
434 def : InstRW<[A57Write_5cyc_2V], (instregex "^(FACGE|FACGT|FCMEQ|FCMGE|FCMGT|FCMLE|FCMLT)(v4f32|v2f64|v4i32|v2i64)")>;
[all...] |
| AArch64SchedCyclone.td | 448 def : InstRW<[CyWriteV3], (instregex "FCMEQ","FCMGT","FCMLE","FCMLT")>;
|
| AArch64InstrInfo.td | 215 def AArch64fcmeq: SDNode<"AArch64ISD::FCMEQ", SDT_AArch64fcmp>;
[all...] |
| AArch64ISelLowering.cpp | [all...] |
| /external/vixl/test/ |
| test-simulator-traces-a64.h | 250 #include "traces/a64/sim-fcmeq-2d-trace-a64.h"
251 #include "traces/a64/sim-fcmeq-2d-2opimm-trace-a64.h"
252 #include "traces/a64/sim-fcmeq-2s-trace-a64.h"
253 #include "traces/a64/sim-fcmeq-2s-2opimm-trace-a64.h"
254 #include "traces/a64/sim-fcmeq-4s-trace-a64.h"
255 #include "traces/a64/sim-fcmeq-4s-2opimm-trace-a64.h"
256 #include "traces/a64/sim-fcmeq-d-trace-a64.h"
257 #include "traces/a64/sim-fcmeq-d-2opimm-trace-a64.h"
258 #include "traces/a64/sim-fcmeq-s-trace-a64.h"
259 #include "traces/a64/sim-fcmeq-s-2opimm-trace-a64.h
[all...] |
| test-simulator-a64.cc | [all...] |
| test-disasm-a64.cc | [all...] |
| /external/clang/test/CodeGen/ |
| aarch64-neon-misc.c | 112 // CHECK: fcmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0
118 // CHECK: fcmeq {{d[0-9]+}}, {{d[0-9]+}}, #0
124 // CHECK: fcmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0
154 // CHECK: fcmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0
[all...] |
| aarch64-neon-intrinsics.c | [all...] |
| /external/valgrind/none/tests/arm64/ |
| fp_and_simd.c | [all...] |
| /external/vixl/doc/ |
| supported-instructions.md | 1743 ### FCMEQ ###
1747 void fcmeq(const VRegister& vd,
1752 ### FCMEQ ###
1756 void fcmeq(const VRegister& vd,
[all...] |
| /external/vixl/src/vixl/a64/ |
| disasm-a64.cc | [all...] |
| macro-assembler-a64.h | [all...] |
