1 //==-- AArch64ISelLowering.h - AArch64 DAG Lowering Interface ----*- C++ -*-==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that AArch64 uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H 16 #define LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H 17 18 #include "llvm/CodeGen/CallingConvLower.h" 19 #include "llvm/CodeGen/SelectionDAG.h" 20 #include "llvm/IR/CallingConv.h" 21 #include "llvm/IR/Instruction.h" 22 #include "llvm/Target/TargetLowering.h" 23 24 namespace llvm { 25 26 namespace AArch64ISD { 27 28 enum { 29 FIRST_NUMBER = ISD::BUILTIN_OP_END, 30 WrapperLarge, // 4-instruction MOVZ/MOVK sequence for 64-bit addresses. 31 CALL, // Function call. 32 33 // Produces the full sequence of instructions for getting the thread pointer 34 // offset of a variable into X0, using the TLSDesc model. 35 TLSDESC_CALLSEQ, 36 ADRP, // Page address of a TargetGlobalAddress operand. 37 ADDlow, // Add the low 12 bits of a TargetGlobalAddress operand. 38 LOADgot, // Load from automatically generated descriptor (e.g. Global 39 // Offset Table, TLS record). 40 RET_FLAG, // Return with a flag operand. Operand 0 is the chain operand. 41 BRCOND, // Conditional branch instruction; "b.cond". 42 CSEL, 43 FCSEL, // Conditional move instruction. 44 CSINV, // Conditional select invert. 45 CSNEG, // Conditional select negate. 46 CSINC, // Conditional select increment. 47 48 // Pointer to the thread's local storage area. Materialised from TPIDR_EL0 on 49 // ELF. 50 THREAD_POINTER, 51 ADC, 52 SBC, // adc, sbc instructions 53 54 // Arithmetic instructions which write flags. 55 ADDS, 56 SUBS, 57 ADCS, 58 SBCS, 59 ANDS, 60 61 // Floating point comparison 62 FCMP, 63 64 // Floating point max and min instructions. 65 FMAX, 66 FMIN, 67 68 // Scalar extract 69 EXTR, 70 71 // Scalar-to-vector duplication 72 DUP, 73 DUPLANE8, 74 DUPLANE16, 75 DUPLANE32, 76 DUPLANE64, 77 78 // Vector immedate moves 79 MOVI, 80 MOVIshift, 81 MOVIedit, 82 MOVImsl, 83 FMOV, 84 MVNIshift, 85 MVNImsl, 86 87 // Vector immediate ops 88 BICi, 89 ORRi, 90 91 // Vector bit select: similar to ISD::VSELECT but not all bits within an 92 // element must be identical. 93 BSL, 94 95 // Vector arithmetic negation 96 NEG, 97 98 // Vector shuffles 99 ZIP1, 100 ZIP2, 101 UZP1, 102 UZP2, 103 TRN1, 104 TRN2, 105 REV16, 106 REV32, 107 REV64, 108 EXT, 109 110 // Vector shift by scalar 111 VSHL, 112 VLSHR, 113 VASHR, 114 115 // Vector shift by scalar (again) 116 SQSHL_I, 117 UQSHL_I, 118 SQSHLU_I, 119 SRSHR_I, 120 URSHR_I, 121 122 // Vector comparisons 123 CMEQ, 124 CMGE, 125 CMGT, 126 CMHI, 127 CMHS, 128 FCMEQ, 129 FCMGE, 130 FCMGT, 131 132 // Vector zero comparisons 133 CMEQz, 134 CMGEz, 135 CMGTz, 136 CMLEz, 137 CMLTz, 138 FCMEQz, 139 FCMGEz, 140 FCMGTz, 141 FCMLEz, 142 FCMLTz, 143 144 // Vector across-lanes addition 145 // Only the lower result lane is defined. 146 SADDV, 147 UADDV, 148 149 // Vector across-lanes min/max 150 // Only the lower result lane is defined. 151 SMINV, 152 UMINV, 153 SMAXV, 154 UMAXV, 155 156 // Vector bitwise negation 157 NOT, 158 159 // Vector bitwise selection 160 BIT, 161 162 // Compare-and-branch 163 CBZ, 164 CBNZ, 165 TBZ, 166 TBNZ, 167 168 // Tail calls 169 TC_RETURN, 170 171 // Custom prefetch handling 172 PREFETCH, 173 174 // {s|u}int to FP within a FP register. 175 SITOF, 176 UITOF, 177 178 /// Natural vector cast. ISD::BITCAST is not natural in the big-endian 179 /// world w.r.t vectors; which causes additional REV instructions to be 180 /// generated to compensate for the byte-swapping. But sometimes we do 181 /// need to re-interpret the data in SIMD vector registers in big-endian 182 /// mode without emitting such REV instructions. 183 NVCAST, 184 185 SMULL, 186 UMULL, 187 188 // NEON Load/Store with post-increment base updates 189 LD2post = ISD::FIRST_TARGET_MEMORY_OPCODE, 190 LD3post, 191 LD4post, 192 ST2post, 193 ST3post, 194 ST4post, 195 LD1x2post, 196 LD1x3post, 197 LD1x4post, 198 ST1x2post, 199 ST1x3post, 200 ST1x4post, 201 LD1DUPpost, 202 LD2DUPpost, 203 LD3DUPpost, 204 LD4DUPpost, 205 LD1LANEpost, 206 LD2LANEpost, 207 LD3LANEpost, 208 LD4LANEpost, 209 ST2LANEpost, 210 ST3LANEpost, 211 ST4LANEpost 212 }; 213 214 } // end namespace AArch64ISD 215 216 class AArch64Subtarget; 217 class AArch64TargetMachine; 218 219 class AArch64TargetLowering : public TargetLowering { 220 bool RequireStrictAlign; 221 222 public: 223 explicit AArch64TargetLowering(const TargetMachine &TM, 224 const AArch64Subtarget &STI); 225 226 /// Selects the correct CCAssignFn for a given CallingConvention value. 227 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const; 228 229 /// computeKnownBitsForTargetNode - Determine which of the bits specified in 230 /// Mask are known to be either zero or one and return them in the 231 /// KnownZero/KnownOne bitsets. 232 void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero, 233 APInt &KnownOne, const SelectionDAG &DAG, 234 unsigned Depth = 0) const override; 235 236 MVT getScalarShiftAmountTy(EVT LHSTy) const override; 237 238 /// allowsMisalignedMemoryAccesses - Returns true if the target allows 239 /// unaligned memory accesses of the specified type. 240 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace = 0, 241 unsigned Align = 1, 242 bool *Fast = nullptr) const override { 243 if (RequireStrictAlign) 244 return false; 245 // FIXME: True for Cyclone, but not necessary others. 246 if (Fast) 247 *Fast = true; 248 return true; 249 } 250 251 /// LowerOperation - Provide custom lowering hooks for some operations. 252 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 253 254 const char *getTargetNodeName(unsigned Opcode) const override; 255 256 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 257 258 /// getFunctionAlignment - Return the Log2 alignment of this function. 259 unsigned getFunctionAlignment(const Function *F) const; 260 261 /// Returns true if a cast between SrcAS and DestAS is a noop. 262 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override { 263 // Addrspacecasts are always noops. 264 return true; 265 } 266 267 /// createFastISel - This method returns a target specific FastISel object, 268 /// or null if the target does not support "fast" ISel. 269 FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 270 const TargetLibraryInfo *libInfo) const override; 271 272 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 273 274 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override; 275 276 /// isShuffleMaskLegal - Return true if the given shuffle mask can be 277 /// codegen'd directly, or if it should be stack expanded. 278 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const override; 279 280 /// getSetCCResultType - Return the ISD::SETCC ValueType 281 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override; 282 283 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const; 284 285 MachineBasicBlock *EmitF128CSEL(MachineInstr *MI, 286 MachineBasicBlock *BB) const; 287 288 MachineBasicBlock * 289 EmitInstrWithCustomInserter(MachineInstr *MI, 290 MachineBasicBlock *MBB) const override; 291 292 bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, 293 unsigned Intrinsic) const override; 294 295 bool isTruncateFree(Type *Ty1, Type *Ty2) const override; 296 bool isTruncateFree(EVT VT1, EVT VT2) const override; 297 298 bool isProfitableToHoist(Instruction *I) const override; 299 300 bool isZExtFree(Type *Ty1, Type *Ty2) const override; 301 bool isZExtFree(EVT VT1, EVT VT2) const override; 302 bool isZExtFree(SDValue Val, EVT VT2) const override; 303 304 bool hasPairedLoad(Type *LoadedType, 305 unsigned &RequiredAligment) const override; 306 bool hasPairedLoad(EVT LoadedType, unsigned &RequiredAligment) const override; 307 308 bool isLegalAddImmediate(int64_t) const override; 309 bool isLegalICmpImmediate(int64_t) const override; 310 311 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, 312 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, 313 MachineFunction &MF) const override; 314 315 /// isLegalAddressingMode - Return true if the addressing mode represented 316 /// by AM is legal for this target, for a load/store of the specified type. 317 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override; 318 319 /// \brief Return the cost of the scaling factor used in the addressing 320 /// mode represented by AM for this target, for a load/store 321 /// of the specified type. 322 /// If the AM is supported, the return value must be >= 0. 323 /// If the AM is not supported, it returns a negative value. 324 int getScalingFactorCost(const AddrMode &AM, Type *Ty) const override; 325 326 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster 327 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be 328 /// expanded to FMAs when this method returns true, otherwise fmuladd is 329 /// expanded to fmul + fadd. 330 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override; 331 332 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override; 333 334 /// \brief Returns false if N is a bit extraction pattern of (X >> C) & Mask. 335 bool isDesirableToCommuteWithShift(const SDNode *N) const override; 336 337 /// \brief Returns true if it is beneficial to convert a load of a constant 338 /// to just the constant itself. 339 bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 340 Type *Ty) const override; 341 342 bool hasLoadLinkedStoreConditional() const override; 343 Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr, 344 AtomicOrdering Ord) const override; 345 Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val, 346 Value *Addr, AtomicOrdering Ord) const override; 347 348 bool shouldExpandAtomicLoadInIR(LoadInst *LI) const override; 349 bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override; 350 TargetLoweringBase::AtomicRMWExpansionKind 351 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override; 352 353 bool useLoadStackGuardNode() const override; 354 TargetLoweringBase::LegalizeTypeAction 355 getPreferredVectorAction(EVT VT) const override; 356 357 private: 358 bool isExtFreeImpl(const Instruction *Ext) const override; 359 360 /// Subtarget - Keep a pointer to the AArch64Subtarget around so that we can 361 /// make the right decision when generating code for different targets. 362 const AArch64Subtarget *Subtarget; 363 364 void addTypeForNEON(EVT VT, EVT PromotedBitwiseVT); 365 void addDRTypeForNEON(MVT VT); 366 void addQRTypeForNEON(MVT VT); 367 368 SDValue 369 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 370 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, 371 SelectionDAG &DAG, 372 SmallVectorImpl<SDValue> &InVals) const override; 373 374 SDValue LowerCall(CallLoweringInfo & /*CLI*/, 375 SmallVectorImpl<SDValue> &InVals) const override; 376 377 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 378 CallingConv::ID CallConv, bool isVarArg, 379 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, 380 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, 381 bool isThisReturn, SDValue ThisVal) const; 382 383 bool isEligibleForTailCallOptimization( 384 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, 385 bool isCalleeStructRet, bool isCallerStructRet, 386 const SmallVectorImpl<ISD::OutputArg> &Outs, 387 const SmallVectorImpl<SDValue> &OutVals, 388 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const; 389 390 /// Finds the incoming stack arguments which overlap the given fixed stack 391 /// object and incorporates their load into the current chain. This prevents 392 /// an upcoming store from clobbering the stack argument before it's used. 393 SDValue addTokenForArgument(SDValue Chain, SelectionDAG &DAG, 394 MachineFrameInfo *MFI, int ClobberedFI) const; 395 396 bool DoesCalleeRestoreStack(CallingConv::ID CallCC, bool TailCallOpt) const; 397 398 bool IsTailCallConvention(CallingConv::ID CallCC) const; 399 400 void saveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG, SDLoc DL, 401 SDValue &Chain) const; 402 403 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 404 bool isVarArg, 405 const SmallVectorImpl<ISD::OutputArg> &Outs, 406 LLVMContext &Context) const override; 407 408 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 409 const SmallVectorImpl<ISD::OutputArg> &Outs, 410 const SmallVectorImpl<SDValue> &OutVals, SDLoc DL, 411 SelectionDAG &DAG) const override; 412 413 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 414 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 415 SDValue LowerDarwinGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 416 SDValue LowerELFGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 417 SDValue LowerELFTLSDescCallSeq(SDValue SymAddr, SDLoc DL, 418 SelectionDAG &DAG) const; 419 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; 420 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 421 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 422 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 423 SDValue LowerSELECT_CC(ISD::CondCode CC, SDValue LHS, SDValue RHS, 424 SDValue TVal, SDValue FVal, SDLoc dl, 425 SelectionDAG &DAG) const; 426 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 427 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 428 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 429 SDValue LowerAAPCS_VASTART(SDValue Op, SelectionDAG &DAG) const; 430 SDValue LowerDarwin_VASTART(SDValue Op, SelectionDAG &DAG) const; 431 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; 432 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const; 433 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const; 434 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 435 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 436 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 437 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 438 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const; 439 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 440 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 441 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; 442 SDValue LowerVectorSRA_SRL_SHL(SDValue Op, SelectionDAG &DAG) const; 443 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const; 444 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const; 445 SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const; 446 SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) const; 447 SDValue LowerF128Call(SDValue Op, SelectionDAG &DAG, 448 RTLIB::Libcall Call) const; 449 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; 450 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const; 451 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const; 452 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const; 453 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 454 SDValue LowerVectorAND(SDValue Op, SelectionDAG &DAG) const; 455 SDValue LowerVectorOR(SDValue Op, SelectionDAG &DAG) const; 456 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const; 457 SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const; 458 459 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, 460 std::vector<SDNode *> *Created) const override; 461 bool combineRepeatedFPDivisors(unsigned NumUsers) const override; 462 463 ConstraintType 464 getConstraintType(const std::string &Constraint) const override; 465 unsigned getRegisterByName(const char* RegName, EVT VT) const override; 466 467 /// Examine constraint string and operand type and determine a weight value. 468 /// The operand object must already have been set up with the operand type. 469 ConstraintWeight 470 getSingleConstraintMatchWeight(AsmOperandInfo &info, 471 const char *constraint) const override; 472 473 std::pair<unsigned, const TargetRegisterClass *> 474 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 475 const std::string &Constraint, 476 MVT VT) const override; 477 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, 478 std::vector<SDValue> &Ops, 479 SelectionDAG &DAG) const override; 480 481 unsigned getInlineAsmMemConstraint( 482 const std::string &ConstraintCode) const override { 483 if (ConstraintCode == "Q") 484 return InlineAsm::Constraint_Q; 485 // FIXME: clang has code for 'Ump', 'Utf', 'Usa', and 'Ush' but these are 486 // followed by llvm_unreachable so we'll leave them unimplemented in 487 // the backend for now. 488 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); 489 } 490 491 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override; 492 bool mayBeEmittedAsTailCall(CallInst *CI) const override; 493 bool getIndexedAddressParts(SDNode *Op, SDValue &Base, SDValue &Offset, 494 ISD::MemIndexedMode &AM, bool &IsInc, 495 SelectionDAG &DAG) const; 496 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, 497 ISD::MemIndexedMode &AM, 498 SelectionDAG &DAG) const override; 499 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, 500 SDValue &Offset, ISD::MemIndexedMode &AM, 501 SelectionDAG &DAG) const override; 502 503 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, 504 SelectionDAG &DAG) const override; 505 506 bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, 507 CallingConv::ID CallConv, 508 bool isVarArg) const override; 509 }; 510 511 namespace AArch64 { 512 FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 513 const TargetLibraryInfo *libInfo); 514 } // end namespace AArch64 515 516 } // end namespace llvm 517 518 #endif 519
