| /external/llvm/test/TableGen/ |
| DefmInsideMultiClass.td | 7 class Instruction<bits<4> opc, string Name> {
8 bits<4> opcode = opc;
12 multiclass basic_r<bits<4> opc> {
13 def rr : Instruction<opc, "rr">;
14 def rm : Instruction<opc, "rm">;
17 multiclass basic_s<bits<4> opc> {
18 defm SS : basic_r<opc>;
19 defm SD : basic_r<opc>;
22 multiclass basic_p<bits<4> opc> {
23 defm PS : basic_r<opc>;
[all...] |
| LetInsideMultiClasses.td | 9 class Instruction<bits<4> opc, string Name> {
10 bits<4> opcode = opc;
15 multiclass basic_r<bits<4> opc> {
17 def rr : Instruction<opc, "rr">;
18 def rm : Instruction<opc, "rm">;
22 def rx : Instruction<opc, "rx">;
25 multiclass basic_ss<bits<4> opc> {
27 defm SS : basic_r<opc>;
30 defm SD : basic_r<opc>;
|
| BitsInit.td | 6 bits<2> opc = { 0, 1 };
9 bits<2> a = { opc, opc2 }; // error!
10 bits<2> b = { opc{0}, opc2{0} };
11 bits<2> c = { opc{1}, opc2{1} };
16 // CHECK: bits<2> opc = { 0, 1 };
|
| /external/llvm/lib/Target/XCore/ |
| XCoreInstrFormats.td | 36 class _F3R<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
38 let Inst{15-11} = opc;
45 class _F3RImm<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
46 : _F3R<opc, outs, ins, asmstr, pattern> {
50 class _FL3R<bits<9> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
52 let Inst{31-27} = opc{8-4};
54 let Inst{19-16} = opc{3-0};
61 class _FL3RSrcDst<bits<9> opc, dag outs, dag ins, string asmstr,
62 list<dag> pattern> : _FL3R<opc, outs, ins, asmstr, pattern> {
66 class _F2RUS<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern
[all...] |
| /external/wpa_supplicant_8/src/crypto/ |
| milenage.h | 12 void milenage_generate(const u8 *opc, const u8 *amf, const u8 *k,
15 int milenage_auts(const u8 *opc, const u8 *k, const u8 *_rand, const u8 *auts,
17 int gsm_milenage(const u8 *opc, const u8 *k, const u8 *_rand, u8 *sres,
19 int milenage_check(const u8 *opc, const u8 *k, const u8 *sqn, const u8 *_rand,
22 int milenage_f1(const u8 *opc, const u8 *k, const u8 *_rand,
24 int milenage_f2345(const u8 *opc, const u8 *k, const u8 *_rand,
|
| milenage.c | 27 * @opc: OPc = 128-bit value derived from OP and K
36 int milenage_f1(const u8 *opc, const u8 *k, const u8 *_rand,
44 tmp1[i] = _rand[i] ^ opc[i];
57 tmp3[(i + 8) % 16] = tmp2[i] ^ opc[i];
67 tmp1[i] ^= opc[i];
78 * @opc: OPc = 128-bit value derived from OP and K
88 int milenage_f2345(const u8 *opc, const u8 *k, const u8 *_rand,
96 tmp1[i] = _rand[i] ^ opc[i]
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 43 unsigned Opc = MI->getOpcode();
45 if ((Opc == Mips::LW) || (Opc == Mips::LD) ||
46 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) {
65 unsigned Opc = MI->getOpcode();
67 if ((Opc == Mips::SW) || (Opc == Mips::SD) ||
68 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164))
[all...] |
| Mips16InstrInfo.cpp | 65 unsigned Opc = 0;
69 Opc = Mips::MoveR3216;
72 Opc = Mips::Move32R16;
75 Opc = Mips::Mfhi16, SrcReg = 0;
79 Opc = Mips::Mflo16, SrcReg = 0;
82 assert(Opc && "Cannot copy registers");
84 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
102 unsigned Opc = 0;
104 Opc = Mips::SwRxSpImmX16;
105 assert(Opc && "Register class not handled!")
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonExpandPredSpillCode.cpp | 81 int Opc = MI->getOpcode();
82 if (Opc == Hexagon::S2_storerb_pci_pseudo ||
83 Opc == Hexagon::S2_storerh_pci_pseudo ||
84 Opc == Hexagon::S2_storeri_pci_pseudo ||
85 Opc == Hexagon::S2_storerd_pci_pseudo ||
86 Opc == Hexagon::S2_storerf_pci_pseudo) {
88 if (Opc == Hexagon::S2_storerd_pci_pseudo)
90 else if (Opc == Hexagon::S2_storeri_pci_pseudo)
92 else if (Opc == Hexagon::S2_storerh_pci_pseudo)
94 else if (Opc == Hexagon::S2_storerf_pci_pseudo
[all...] |
| HexagonCFGOptimizer.cpp | 57 static bool IsConditionalBranch(int Opc) {
58 return (Opc == Hexagon::J2_jumpt) || (Opc == Hexagon::J2_jumpf)
59 || (Opc == Hexagon::J2_jumptnewpt) || (Opc == Hexagon::J2_jumpfnewpt);
63 static bool IsUnconditionalJump(int Opc) {
64 return (Opc == Hexagon::J2_jump);
110 int Opc = MI->getOpcode();
111 if (IsConditionalBranch(Opc)) {
|
| HexagonSplitConst32AndConst64.cpp | 85 int Opc = MI->getOpcode();
86 if (Opc == Hexagon::CONST32_set_jt) {
97 else if (Opc == Hexagon::CONST32_Int_Real &&
112 else if (Opc == Hexagon::CONST32_Int_Real ||
113 Opc == Hexagon::CONST32_Float_Real) {
119 if (Opc == Hexagon::CONST32_Float_Real) {
131 else if (Opc == Hexagon::CONST64_Int_Real ||
132 Opc == Hexagon::CONST64_Float_Real) {
138 if (Opc == Hexagon::CONST64_Float_Real) {
|
| /external/llvm/lib/Target/ARM/ |
| ARMInstrFormats.td | 420 string opc, string asm, string cstr,
427 let AsmString = !strconcat(opc, "${p}", asm);
435 string opc, string asm, string cstr,
440 let AsmString = !strconcat(opc, asm);
451 string opc, string asm, string cstr,
461 let AsmString = !strconcat(opc, "${s}${p}", asm);
479 string opc, string asm, list<dag> pattern>
481 opc, asm, "", pattern>;
483 string opc, string asm, list<dag> pattern>
485 opc, asm, "", pattern>
[all...] |
| ARMBaseInstrInfo.h | 93 // Return the non-pre/post incrementing version of 'Opc'. Return 0
95 virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
406 bool isUncondBranchOpcode(int Opc) {
407 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
411 bool isCondBranchOpcode(int Opc) {
412 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc
[all...] |
| ARMInstrInfo.cpp | 52 unsigned ARMInstrInfo::getUnindexedOpcode(unsigned Opc) const {
53 switch (Opc) {
171 unsigned Opc = STI.isThumb2() ? ARM::t2LDRpci : ARM::LDRcp;
174 TII.get(Opc), TempReg)
176 if (Opc == ARM::LDRcp)
182 Opc = STI.isThumb2() ? ARM::tPICADD : ARM::PICADD;
183 MIB = BuildMI(FirstMBB, MBBI, DL, TII.get(Opc), GlobalBaseReg)
186 if (Opc == ARM::PICADD)
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelDAGToDAG.cpp | 576 unsigned Opc;
580 Opc = TM.is64Bit() ? NVPTX::cvta_global_yes_64 : NVPTX::cvta_global_yes;
583 Opc = TM.is64Bit() ? NVPTX::cvta_shared_yes_64 : NVPTX::cvta_shared_yes;
586 Opc = TM.is64Bit() ? NVPTX::cvta_const_yes_64 : NVPTX::cvta_const_yes;
589 Opc = TM.is64Bit() ? NVPTX::cvta_local_yes_64 : NVPTX::cvta_local_yes;
592 return CurDAG->getMachineNode(Opc, SDLoc(N), N->getValueType(0), Src);
597 unsigned Opc;
601 Opc = TM.is64Bit() ? NVPTX::cvta_to_global_yes_64
605 Opc = TM.is64Bit() ? NVPTX::cvta_to_shared_yes_64
609 Opc
[all...] |
| /external/wpa_supplicant_8/hostapd/ |
| hlr_auc_gw.milenage_db | 2 # The example Ki, OPc, and AMF values here are from 3GPP TS 35.208 v6.0.0
8 # IMSI Ki OPc AMF SQN [RES_len]
|
| /external/valgrind/auxprogs/ |
| s390-check-opcodes.pl | 8 # It utilizes <binutils>/opcodes/s390-opc.txt and
10 # - identify new opcodes that are present in s390-opc.txt
11 # (s390-opc.txt is the golden list)
18 die "usage: s390-check-opcodes s390-opcodes.csv s390-opc.txt guest_s390_toIR.c\n";
33 # Read s390-opc.txt (binutils)
35 open(OPC, "$opc_file") || die "cannot open $opc_file\n";
36 while (my $line = <OPC>) {
116 close(OPC);
202 foreach my $opc (keys %opc_desc) {
203 if (! $csv_desc{$opc}) {
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86Instr3DNow.td | 36 multiclass I3DNow_binop_rm<bits<8> opc, string Mn> {
37 def rr : I3DNow_binop<opc, MRMSrcReg, (ins VR64:$src1, VR64:$src2), Mn, []>;
38 def rm : I3DNow_binop<opc, MRMSrcMem, (ins VR64:$src1, i64mem:$src2), Mn, []>;
41 multiclass I3DNow_binop_rm_int<bits<8> opc, string Mn, string Ver = ""> {
42 def rr : I3DNow_binop<opc, MRMSrcReg, (ins VR64:$src1, VR64:$src2), Mn,
45 def rm : I3DNow_binop<opc, MRMSrcMem, (ins VR64:$src1, i64mem:$src2), Mn,
51 multiclass I3DNow_conv_rm<bits<8> opc, string Mn> {
52 def rr : I3DNow_conv<opc, MRMSrcReg, (ins VR64:$src1), Mn, []>;
53 def rm : I3DNow_conv<opc, MRMSrcMem, (ins i64mem:$src1), Mn, []>;
56 multiclass I3DNow_conv_rm_int<bits<8> opc, string Mn, string Ver = "">
[all...] |
| X86InstrXOP.td | 14 multiclass xop2op<bits<8> opc, string OpcodeStr, Intrinsic Int, PatFrag memop> {
15 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
18 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
42 multiclass xop2opsld<bits<8> opc, string OpcodeStr, Intrinsic Int,
44 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
47 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins memop:$src),
52 multiclass xop2op128<bits<8> opc, string OpcodeStr, Intrinsic Int,
54 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
57 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
62 multiclass xop2op256<bits<8> opc, string OpcodeStr, Intrinsic Int
[all...] |
| X86InstrAVX512.td | [all...] |
| X86InstrCMovSetCC.td | 17 multiclass CMOV<bits<8> opc, string Mnemonic, PatLeaf CondNode> {
21 : I<opc, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
27 : I<opc, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
33 :RI<opc, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
43 : I<opc, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
49 : I<opc, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
55 :RI<opc, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
83 multiclass SETCC<bits<8> opc, string Mnemonic, PatLeaf OpNode> {
85 def r : I<opc, MRMXr, (outs GR8:$dst), (ins),
89 def m : I<opc, MRMXm, (outs), (ins i8mem:$dst)
[all...] |
| X86InstrFMA.td | 19 multiclass fma3p_rm<bits<8> opc, string OpcodeStr,
25 def r : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
33 def m : FMA3<opc, MRMSrcMem, (outs VR128:$dst),
41 def rY : FMA3<opc, MRMSrcReg, (outs VR256:$dst),
49 def mY : FMA3<opc, MRMSrcMem, (outs VR256:$dst),
130 multiclass fma3s_rm<bits<8> opc, string OpcodeStr, X86MemOperand x86memop,
135 def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
143 def m : FMA3<opc, MRMSrcMem, (outs RC:$dst),
219 multiclass fma4s<bits<8> opc, string OpcodeStr, RegisterClass RC,
223 def rr : FMA4<opc, MRMSrcReg, (outs RC:$dst)
[all...] |
| /bionic/libc/upstream-netbsd/lib/libc/regex/ |
| regex2.h | 121 #define OPC(n) (((u_int32_t)(n))<<OPSHIFT)
124 #define OEND OPC(1) /* endmarker - */
125 #define OCHAR OPC(2) /* character unsigned char */
126 #define OBOL OPC(3) /* left anchor - */
127 #define OEOL OPC(4) /* right anchor - */
128 #define OANY OPC(5) /* . - */
129 #define OANYOF OPC(6) /* [...] set number */
130 #define OBACK_ OPC(7) /* begin \d paren number */
131 #define O_BACK OPC(8) /* end \d paren number */
132 #define OPLUS_ OPC(9) /* + prefix fwd to suffix *
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrFormats.td | 829 class CRmSystemI<Operand crmtype, bits<3> opc, string asm,
836 let Inst{7-5} = opc;
948 // case opc of
955 class BaseBranchReg<bits<4> opc, dag oops, dag iops, string asm,
959 let Inst{24-21} = opc;
965 class BranchReg<bits<4> opc, string asm, list<dag> pattern>
966 : BaseBranchReg<opc, (outs), (ins GPR64:$Rn), asm, "\t$Rn", pattern> {
972 class SpecialReturn<bits<4> opc, string asm>
973 : BaseBranchReg<opc, (outs), (ins), asm, "", []> {
[all...] |
| /external/llvm/docs/TableGen/ |
| LangIntro.rst | 387 class inst<int opc, string asmstr, dag operandlist>;
389 multiclass ri_inst<int opc, string asmstr> {
390 def _rr : inst<opc, !strconcat(asmstr, " $dst, $src1, $src2"),
392 def _ri : inst<opc, !strconcat(asmstr, " $dst, $src1, $src2"),
413 class inst<int opc, string asmstr, dag operandlist>;
415 class rrinst<int opc, string asmstr>
416 : inst<opc, !strconcat(asmstr, " $dst, $src1, $src2"),
419 class riinst<int opc, string asmstr>
420 : inst<opc, !strconcat(asmstr, " $dst, $src1, $src2"),
437 class Instruction<bits<4> opc, string Name>
[all...] |
