| /external/llvm/test/CodeGen/AArch64/ |
| arm64-smaxv.ll | 5 ; CHECK: smaxv.8b b[[REGNUM:[0-9]+]], v0
9 %vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i8(<8 x i8> %a1)
16 ; CHECK: smaxv.4h h[[REGNUM:[0-9]+]], v0
20 %vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v4i16(<4 x i16> %a1)
32 %vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v2i32(<2 x i32> %a1)
38 ; CHECK: smaxv.16b b[[REGNUM:[0-9]+]], v0
42 %vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v16i8(<16 x i8> %a1)
49 ; CHECK: smaxv.8h h[[REGNUM:[0-9]+]], v0
53 %vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i16(<8 x i16> %a1)
60 ; CHECK: smaxv.4s [[REGNUM:s[0-9]+]], v
[all...] |
| arm64-neon-across.ll | 47 declare i32 @llvm.aarch64.neon.smaxv.i32.v4i32(<4 x i32>)
49 declare i32 @llvm.aarch64.neon.smaxv.i32.v8i16(<8 x i16>)
51 declare i32 @llvm.aarch64.neon.smaxv.i32.v16i8(<16 x i8>)
57 declare i32 @llvm.aarch64.neon.smaxv.i32.v4i16(<4 x i16>)
59 declare i32 @llvm.aarch64.neon.smaxv.i32.v8i8(<8 x i8>)
167 ; CHECK: smaxv b{{[0-9]+}}, {{v[0-9]+}}.8b
169 %smaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i8(<8 x i8> %a)
170 %0 = trunc i32 %smaxv.i to i8
176 ; CHECK: smaxv h{{[0-9]+}}, {{v[0-9]+}}.4
[all...] |
| /external/llvm/test/MC/AArch64/ |
| neon-across.s | 33 smaxv b0, v1.8b
34 smaxv b0, v1.16b
35 smaxv h0, v1.4h
36 smaxv h0, v1.8h
37 smaxv s0, v1.4s
39 // CHECK: smaxv b0, v1.8b // encoding: [0x20,0xa8,0x30,0x0e]
40 // CHECK: smaxv b0, v1.16b // encoding: [0x20,0xa8,0x30,0x4e]
41 // CHECK: smaxv h0, v1.4h // encoding: [0x20,0xa8,0x70,0x0e]
42 // CHECK: smaxv h0, v1.8h // encoding: [0x20,0xa8,0x70,0x4e]
43 // CHECK: smaxv s0, v1.4s // encoding: [0x20,0xa8,0xb0,0x4e
[all...] |
| neon-diagnostics.s | [all...] |
| /external/clang/test/CodeGen/ |
| arm64_vset_lane.c | 25 // CHECK@ @llvm.aarch64.neon.smaxv.i32.v8i8
|
| aarch64-neon-across.c | 72 // CHECK: smaxv {{b[0-9]+}}, {{v[0-9]+}}.8b
78 // CHECK: smaxv {{h[0-9]+}}, {{v[0-9]+}}.4h
96 // CHECK: smaxv {{b[0-9]+}}, {{v[0-9]+}}.16b
102 // CHECK: smaxv {{h[0-9]+}}, {{v[0-9]+}}.8h
108 // CHECK: smaxv {{s[0-9]+}}, {{v[0-9]+}}.4s
|
| arm64_vMaxMin.c | 12 // CHECK: call i32 @llvm.aarch64.neon.smaxv.i32.v8i8(
114 // CHECK: call i32 @llvm.aarch64.neon.smaxv.i32.v2i32(
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.h | 153 SMAXV,
|
| AArch64SchedCyclone.td | 419 def : InstRW<[CyWriteV3], (instregex "SMAXv","SMINv","UMAXv","UMINv",
|
| AArch64InstrInfo.td | 267 def AArch64smaxv : SDNode<"AArch64ISD::SMAXV", SDT_AArch64UnaryVec>;
[all...] |
| AArch64ISelLowering.cpp | [all...] |
| /external/valgrind/none/tests/arm64/ |
| fp_and_simd.stdout.exp | [all...] |
| fp_and_simd.c | 1013 "smaxv s8, v7.4s ; "
1017 printf("SMAXV v8, v7.4s ");
1030 "smaxv h8, v7.8h ; "
1034 printf("SMAXV h8, v7.8h ");
1047 "smaxv h8, v7.4h ; "
1051 printf("SMAXV h8, v7.4h ");
1064 "smaxv b8, v7.16b ; "
1068 printf("SMAXV b8, v7.16b ");
1081 "smaxv b8, v7.8b ; "
1085 printf("SMAXV b8, v7.8b ")
[all...] |
| /external/vixl/test/ |
| test-simulator-traces-a64.h | [all...] |
| test-disasm-a64.cc | [all...] |
| test-simulator-a64.cc | [all...] |
| /external/vixl/doc/ |
| supported-instructions.md | [all...] |
| /external/vixl/src/vixl/a64/ |
| macro-assembler-a64.h | [all...] |
| disasm-a64.cc | [all...] |
| simulator-a64.h | [all...] |
| assembler-a64.h | [all...] |
| logic-a64.cc | 1470 LogicVRegister Simulator::smaxv(VectorFormat vform, function in class:vixl::Simulator
[all...] |
| simulator-a64.cc | [all...] |
| assembler-a64.cc | [all...] |
| /external/valgrind/VEX/priv/ |
| guest_arm64_toIR.c | [all...] |
