1 //===-- AArch64BaseInfo.cpp - AArch64 Base encoding information------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file provides basic encoding and assembly information for AArch64. 11 // 12 //===----------------------------------------------------------------------===// 13 #include "AArch64BaseInfo.h" 14 #include "llvm/ADT/APFloat.h" 15 #include "llvm/ADT/SmallVector.h" 16 #include "llvm/ADT/StringExtras.h" 17 #include "llvm/Support/Regex.h" 18 19 using namespace llvm; 20 21 StringRef AArch64NamedImmMapper::toString(uint32_t Value, uint64_t FeatureBits, 22 bool &Valid) const { 23 for (unsigned i = 0; i < NumMappings; ++i) { 24 if (Mappings[i].isValueEqual(Value, FeatureBits)) { 25 Valid = true; 26 return Mappings[i].Name; 27 } 28 } 29 30 Valid = false; 31 return StringRef(); 32 } 33 34 uint32_t AArch64NamedImmMapper::fromString(StringRef Name, uint64_t FeatureBits, 35 bool &Valid) const { 36 std::string LowerCaseName = Name.lower(); 37 for (unsigned i = 0; i < NumMappings; ++i) { 38 if (Mappings[i].isNameEqual(LowerCaseName, FeatureBits)) { 39 Valid = true; 40 return Mappings[i].Value; 41 } 42 } 43 44 Valid = false; 45 return -1; 46 } 47 48 bool AArch64NamedImmMapper::validImm(uint32_t Value) const { 49 return Value < TooBigImm; 50 } 51 52 const AArch64NamedImmMapper::Mapping AArch64AT::ATMapper::ATMappings[] = { 53 {"s1e1r", S1E1R, 0}, 54 {"s1e2r", S1E2R, 0}, 55 {"s1e3r", S1E3R, 0}, 56 {"s1e1w", S1E1W, 0}, 57 {"s1e2w", S1E2W, 0}, 58 {"s1e3w", S1E3W, 0}, 59 {"s1e0r", S1E0R, 0}, 60 {"s1e0w", S1E0W, 0}, 61 {"s12e1r", S12E1R, 0}, 62 {"s12e1w", S12E1W, 0}, 63 {"s12e0r", S12E0R, 0}, 64 {"s12e0w", S12E0W, 0}, 65 }; 66 67 AArch64AT::ATMapper::ATMapper() 68 : AArch64NamedImmMapper(ATMappings, 0) {} 69 70 const AArch64NamedImmMapper::Mapping AArch64DB::DBarrierMapper::DBarrierMappings[] = { 71 {"oshld", OSHLD, 0}, 72 {"oshst", OSHST, 0}, 73 {"osh", OSH, 0}, 74 {"nshld", NSHLD, 0}, 75 {"nshst", NSHST, 0}, 76 {"nsh", NSH, 0}, 77 {"ishld", ISHLD, 0}, 78 {"ishst", ISHST, 0}, 79 {"ish", ISH, 0}, 80 {"ld", LD, 0}, 81 {"st", ST, 0}, 82 {"sy", SY, 0} 83 }; 84 85 AArch64DB::DBarrierMapper::DBarrierMapper() 86 : AArch64NamedImmMapper(DBarrierMappings, 16u) {} 87 88 const AArch64NamedImmMapper::Mapping AArch64DC::DCMapper::DCMappings[] = { 89 {"zva", ZVA, 0}, 90 {"ivac", IVAC, 0}, 91 {"isw", ISW, 0}, 92 {"cvac", CVAC, 0}, 93 {"csw", CSW, 0}, 94 {"cvau", CVAU, 0}, 95 {"civac", CIVAC, 0}, 96 {"cisw", CISW, 0} 97 }; 98 99 AArch64DC::DCMapper::DCMapper() 100 : AArch64NamedImmMapper(DCMappings, 0) {} 101 102 const AArch64NamedImmMapper::Mapping AArch64IC::ICMapper::ICMappings[] = { 103 {"ialluis", IALLUIS, 0}, 104 {"iallu", IALLU, 0}, 105 {"ivau", IVAU, 0} 106 }; 107 108 AArch64IC::ICMapper::ICMapper() 109 : AArch64NamedImmMapper(ICMappings, 0) {} 110 111 const AArch64NamedImmMapper::Mapping AArch64ISB::ISBMapper::ISBMappings[] = { 112 {"sy", SY, 0}, 113 }; 114 115 AArch64ISB::ISBMapper::ISBMapper() 116 : AArch64NamedImmMapper(ISBMappings, 16) {} 117 118 const AArch64NamedImmMapper::Mapping AArch64PRFM::PRFMMapper::PRFMMappings[] = { 119 {"pldl1keep", PLDL1KEEP, 0}, 120 {"pldl1strm", PLDL1STRM, 0}, 121 {"pldl2keep", PLDL2KEEP, 0}, 122 {"pldl2strm", PLDL2STRM, 0}, 123 {"pldl3keep", PLDL3KEEP, 0}, 124 {"pldl3strm", PLDL3STRM, 0}, 125 {"plil1keep", PLIL1KEEP, 0}, 126 {"plil1strm", PLIL1STRM, 0}, 127 {"plil2keep", PLIL2KEEP, 0}, 128 {"plil2strm", PLIL2STRM, 0}, 129 {"plil3keep", PLIL3KEEP, 0}, 130 {"plil3strm", PLIL3STRM, 0}, 131 {"pstl1keep", PSTL1KEEP, 0}, 132 {"pstl1strm", PSTL1STRM, 0}, 133 {"pstl2keep", PSTL2KEEP, 0}, 134 {"pstl2strm", PSTL2STRM, 0}, 135 {"pstl3keep", PSTL3KEEP, 0}, 136 {"pstl3strm", PSTL3STRM, 0} 137 }; 138 139 AArch64PRFM::PRFMMapper::PRFMMapper() 140 : AArch64NamedImmMapper(PRFMMappings, 32) {} 141 142 const AArch64NamedImmMapper::Mapping AArch64PState::PStateMapper::PStateMappings[] = { 143 {"spsel", SPSel, 0}, 144 {"daifset", DAIFSet, 0}, 145 {"daifclr", DAIFClr, 0}, 146 147 // v8.1a "Privileged Access Never" extension-specific PStates 148 {"pan", PAN, AArch64::HasV8_1aOps}, 149 }; 150 151 AArch64PState::PStateMapper::PStateMapper() 152 : AArch64NamedImmMapper(PStateMappings, 0) {} 153 154 const AArch64NamedImmMapper::Mapping AArch64SysReg::MRSMapper::MRSMappings[] = { 155 {"mdccsr_el0", MDCCSR_EL0, 0}, 156 {"dbgdtrrx_el0", DBGDTRRX_EL0, 0}, 157 {"mdrar_el1", MDRAR_EL1, 0}, 158 {"oslsr_el1", OSLSR_EL1, 0}, 159 {"dbgauthstatus_el1", DBGAUTHSTATUS_EL1, 0}, 160 {"pmceid0_el0", PMCEID0_EL0, 0}, 161 {"pmceid1_el0", PMCEID1_EL0, 0}, 162 {"midr_el1", MIDR_EL1, 0}, 163 {"ccsidr_el1", CCSIDR_EL1, 0}, 164 {"clidr_el1", CLIDR_EL1, 0}, 165 {"ctr_el0", CTR_EL0, 0}, 166 {"mpidr_el1", MPIDR_EL1, 0}, 167 {"revidr_el1", REVIDR_EL1, 0}, 168 {"aidr_el1", AIDR_EL1, 0}, 169 {"dczid_el0", DCZID_EL0, 0}, 170 {"id_pfr0_el1", ID_PFR0_EL1, 0}, 171 {"id_pfr1_el1", ID_PFR1_EL1, 0}, 172 {"id_dfr0_el1", ID_DFR0_EL1, 0}, 173 {"id_afr0_el1", ID_AFR0_EL1, 0}, 174 {"id_mmfr0_el1", ID_MMFR0_EL1, 0}, 175 {"id_mmfr1_el1", ID_MMFR1_EL1, 0}, 176 {"id_mmfr2_el1", ID_MMFR2_EL1, 0}, 177 {"id_mmfr3_el1", ID_MMFR3_EL1, 0}, 178 {"id_isar0_el1", ID_ISAR0_EL1, 0}, 179 {"id_isar1_el1", ID_ISAR1_EL1, 0}, 180 {"id_isar2_el1", ID_ISAR2_EL1, 0}, 181 {"id_isar3_el1", ID_ISAR3_EL1, 0}, 182 {"id_isar4_el1", ID_ISAR4_EL1, 0}, 183 {"id_isar5_el1", ID_ISAR5_EL1, 0}, 184 {"id_aa64pfr0_el1", ID_A64PFR0_EL1, 0}, 185 {"id_aa64pfr1_el1", ID_A64PFR1_EL1, 0}, 186 {"id_aa64dfr0_el1", ID_A64DFR0_EL1, 0}, 187 {"id_aa64dfr1_el1", ID_A64DFR1_EL1, 0}, 188 {"id_aa64afr0_el1", ID_A64AFR0_EL1, 0}, 189 {"id_aa64afr1_el1", ID_A64AFR1_EL1, 0}, 190 {"id_aa64isar0_el1", ID_A64ISAR0_EL1, 0}, 191 {"id_aa64isar1_el1", ID_A64ISAR1_EL1, 0}, 192 {"id_aa64mmfr0_el1", ID_A64MMFR0_EL1, 0}, 193 {"id_aa64mmfr1_el1", ID_A64MMFR1_EL1, 0}, 194 {"mvfr0_el1", MVFR0_EL1, 0}, 195 {"mvfr1_el1", MVFR1_EL1, 0}, 196 {"mvfr2_el1", MVFR2_EL1, 0}, 197 {"rvbar_el1", RVBAR_EL1, 0}, 198 {"rvbar_el2", RVBAR_EL2, 0}, 199 {"rvbar_el3", RVBAR_EL3, 0}, 200 {"isr_el1", ISR_EL1, 0}, 201 {"cntpct_el0", CNTPCT_EL0, 0}, 202 {"cntvct_el0", CNTVCT_EL0, 0}, 203 204 // Trace registers 205 {"trcstatr", TRCSTATR, 0}, 206 {"trcidr8", TRCIDR8, 0}, 207 {"trcidr9", TRCIDR9, 0}, 208 {"trcidr10", TRCIDR10, 0}, 209 {"trcidr11", TRCIDR11, 0}, 210 {"trcidr12", TRCIDR12, 0}, 211 {"trcidr13", TRCIDR13, 0}, 212 {"trcidr0", TRCIDR0, 0}, 213 {"trcidr1", TRCIDR1, 0}, 214 {"trcidr2", TRCIDR2, 0}, 215 {"trcidr3", TRCIDR3, 0}, 216 {"trcidr4", TRCIDR4, 0}, 217 {"trcidr5", TRCIDR5, 0}, 218 {"trcidr6", TRCIDR6, 0}, 219 {"trcidr7", TRCIDR7, 0}, 220 {"trcoslsr", TRCOSLSR, 0}, 221 {"trcpdsr", TRCPDSR, 0}, 222 {"trcdevaff0", TRCDEVAFF0, 0}, 223 {"trcdevaff1", TRCDEVAFF1, 0}, 224 {"trclsr", TRCLSR, 0}, 225 {"trcauthstatus", TRCAUTHSTATUS, 0}, 226 {"trcdevarch", TRCDEVARCH, 0}, 227 {"trcdevid", TRCDEVID, 0}, 228 {"trcdevtype", TRCDEVTYPE, 0}, 229 {"trcpidr4", TRCPIDR4, 0}, 230 {"trcpidr5", TRCPIDR5, 0}, 231 {"trcpidr6", TRCPIDR6, 0}, 232 {"trcpidr7", TRCPIDR7, 0}, 233 {"trcpidr0", TRCPIDR0, 0}, 234 {"trcpidr1", TRCPIDR1, 0}, 235 {"trcpidr2", TRCPIDR2, 0}, 236 {"trcpidr3", TRCPIDR3, 0}, 237 {"trccidr0", TRCCIDR0, 0}, 238 {"trccidr1", TRCCIDR1, 0}, 239 {"trccidr2", TRCCIDR2, 0}, 240 {"trccidr3", TRCCIDR3, 0}, 241 242 // GICv3 registers 243 {"icc_iar1_el1", ICC_IAR1_EL1, 0}, 244 {"icc_iar0_el1", ICC_IAR0_EL1, 0}, 245 {"icc_hppir1_el1", ICC_HPPIR1_EL1, 0}, 246 {"icc_hppir0_el1", ICC_HPPIR0_EL1, 0}, 247 {"icc_rpr_el1", ICC_RPR_EL1, 0}, 248 {"ich_vtr_el2", ICH_VTR_EL2, 0}, 249 {"ich_eisr_el2", ICH_EISR_EL2, 0}, 250 {"ich_elsr_el2", ICH_ELSR_EL2, 0} 251 }; 252 253 AArch64SysReg::MRSMapper::MRSMapper() { 254 InstMappings = &MRSMappings[0]; 255 NumInstMappings = llvm::array_lengthof(MRSMappings); 256 } 257 258 const AArch64NamedImmMapper::Mapping AArch64SysReg::MSRMapper::MSRMappings[] = { 259 {"dbgdtrtx_el0", DBGDTRTX_EL0, 0}, 260 {"oslar_el1", OSLAR_EL1, 0}, 261 {"pmswinc_el0", PMSWINC_EL0, 0}, 262 263 // Trace registers 264 {"trcoslar", TRCOSLAR, 0}, 265 {"trclar", TRCLAR, 0}, 266 267 // GICv3 registers 268 {"icc_eoir1_el1", ICC_EOIR1_EL1, 0}, 269 {"icc_eoir0_el1", ICC_EOIR0_EL1, 0}, 270 {"icc_dir_el1", ICC_DIR_EL1, 0}, 271 {"icc_sgi1r_el1", ICC_SGI1R_EL1, 0}, 272 {"icc_asgi1r_el1", ICC_ASGI1R_EL1, 0}, 273 {"icc_sgi0r_el1", ICC_SGI0R_EL1, 0}, 274 275 // v8.1a "Privileged Access Never" extension-specific system registers 276 {"pan", PAN, AArch64::HasV8_1aOps}, 277 }; 278 279 AArch64SysReg::MSRMapper::MSRMapper() { 280 InstMappings = &MSRMappings[0]; 281 NumInstMappings = llvm::array_lengthof(MSRMappings); 282 } 283 284 285 const AArch64NamedImmMapper::Mapping AArch64SysReg::SysRegMapper::SysRegMappings[] = { 286 {"osdtrrx_el1", OSDTRRX_EL1, 0}, 287 {"osdtrtx_el1", OSDTRTX_EL1, 0}, 288 {"teecr32_el1", TEECR32_EL1, 0}, 289 {"mdccint_el1", MDCCINT_EL1, 0}, 290 {"mdscr_el1", MDSCR_EL1, 0}, 291 {"dbgdtr_el0", DBGDTR_EL0, 0}, 292 {"oseccr_el1", OSECCR_EL1, 0}, 293 {"dbgvcr32_el2", DBGVCR32_EL2, 0}, 294 {"dbgbvr0_el1", DBGBVR0_EL1, 0}, 295 {"dbgbvr1_el1", DBGBVR1_EL1, 0}, 296 {"dbgbvr2_el1", DBGBVR2_EL1, 0}, 297 {"dbgbvr3_el1", DBGBVR3_EL1, 0}, 298 {"dbgbvr4_el1", DBGBVR4_EL1, 0}, 299 {"dbgbvr5_el1", DBGBVR5_EL1, 0}, 300 {"dbgbvr6_el1", DBGBVR6_EL1, 0}, 301 {"dbgbvr7_el1", DBGBVR7_EL1, 0}, 302 {"dbgbvr8_el1", DBGBVR8_EL1, 0}, 303 {"dbgbvr9_el1", DBGBVR9_EL1, 0}, 304 {"dbgbvr10_el1", DBGBVR10_EL1, 0}, 305 {"dbgbvr11_el1", DBGBVR11_EL1, 0}, 306 {"dbgbvr12_el1", DBGBVR12_EL1, 0}, 307 {"dbgbvr13_el1", DBGBVR13_EL1, 0}, 308 {"dbgbvr14_el1", DBGBVR14_EL1, 0}, 309 {"dbgbvr15_el1", DBGBVR15_EL1, 0}, 310 {"dbgbcr0_el1", DBGBCR0_EL1, 0}, 311 {"dbgbcr1_el1", DBGBCR1_EL1, 0}, 312 {"dbgbcr2_el1", DBGBCR2_EL1, 0}, 313 {"dbgbcr3_el1", DBGBCR3_EL1, 0}, 314 {"dbgbcr4_el1", DBGBCR4_EL1, 0}, 315 {"dbgbcr5_el1", DBGBCR5_EL1, 0}, 316 {"dbgbcr6_el1", DBGBCR6_EL1, 0}, 317 {"dbgbcr7_el1", DBGBCR7_EL1, 0}, 318 {"dbgbcr8_el1", DBGBCR8_EL1, 0}, 319 {"dbgbcr9_el1", DBGBCR9_EL1, 0}, 320 {"dbgbcr10_el1", DBGBCR10_EL1, 0}, 321 {"dbgbcr11_el1", DBGBCR11_EL1, 0}, 322 {"dbgbcr12_el1", DBGBCR12_EL1, 0}, 323 {"dbgbcr13_el1", DBGBCR13_EL1, 0}, 324 {"dbgbcr14_el1", DBGBCR14_EL1, 0}, 325 {"dbgbcr15_el1", DBGBCR15_EL1, 0}, 326 {"dbgwvr0_el1", DBGWVR0_EL1, 0}, 327 {"dbgwvr1_el1", DBGWVR1_EL1, 0}, 328 {"dbgwvr2_el1", DBGWVR2_EL1, 0}, 329 {"dbgwvr3_el1", DBGWVR3_EL1, 0}, 330 {"dbgwvr4_el1", DBGWVR4_EL1, 0}, 331 {"dbgwvr5_el1", DBGWVR5_EL1, 0}, 332 {"dbgwvr6_el1", DBGWVR6_EL1, 0}, 333 {"dbgwvr7_el1", DBGWVR7_EL1, 0}, 334 {"dbgwvr8_el1", DBGWVR8_EL1, 0}, 335 {"dbgwvr9_el1", DBGWVR9_EL1, 0}, 336 {"dbgwvr10_el1", DBGWVR10_EL1, 0}, 337 {"dbgwvr11_el1", DBGWVR11_EL1, 0}, 338 {"dbgwvr12_el1", DBGWVR12_EL1, 0}, 339 {"dbgwvr13_el1", DBGWVR13_EL1, 0}, 340 {"dbgwvr14_el1", DBGWVR14_EL1, 0}, 341 {"dbgwvr15_el1", DBGWVR15_EL1, 0}, 342 {"dbgwcr0_el1", DBGWCR0_EL1, 0}, 343 {"dbgwcr1_el1", DBGWCR1_EL1, 0}, 344 {"dbgwcr2_el1", DBGWCR2_EL1, 0}, 345 {"dbgwcr3_el1", DBGWCR3_EL1, 0}, 346 {"dbgwcr4_el1", DBGWCR4_EL1, 0}, 347 {"dbgwcr5_el1", DBGWCR5_EL1, 0}, 348 {"dbgwcr6_el1", DBGWCR6_EL1, 0}, 349 {"dbgwcr7_el1", DBGWCR7_EL1, 0}, 350 {"dbgwcr8_el1", DBGWCR8_EL1, 0}, 351 {"dbgwcr9_el1", DBGWCR9_EL1, 0}, 352 {"dbgwcr10_el1", DBGWCR10_EL1, 0}, 353 {"dbgwcr11_el1", DBGWCR11_EL1, 0}, 354 {"dbgwcr12_el1", DBGWCR12_EL1, 0}, 355 {"dbgwcr13_el1", DBGWCR13_EL1, 0}, 356 {"dbgwcr14_el1", DBGWCR14_EL1, 0}, 357 {"dbgwcr15_el1", DBGWCR15_EL1, 0}, 358 {"teehbr32_el1", TEEHBR32_EL1, 0}, 359 {"osdlr_el1", OSDLR_EL1, 0}, 360 {"dbgprcr_el1", DBGPRCR_EL1, 0}, 361 {"dbgclaimset_el1", DBGCLAIMSET_EL1, 0}, 362 {"dbgclaimclr_el1", DBGCLAIMCLR_EL1, 0}, 363 {"csselr_el1", CSSELR_EL1, 0}, 364 {"vpidr_el2", VPIDR_EL2, 0}, 365 {"vmpidr_el2", VMPIDR_EL2, 0}, 366 {"sctlr_el1", SCTLR_EL1, 0}, 367 {"sctlr_el2", SCTLR_EL2, 0}, 368 {"sctlr_el3", SCTLR_EL3, 0}, 369 {"actlr_el1", ACTLR_EL1, 0}, 370 {"actlr_el2", ACTLR_EL2, 0}, 371 {"actlr_el3", ACTLR_EL3, 0}, 372 {"cpacr_el1", CPACR_EL1, 0}, 373 {"hcr_el2", HCR_EL2, 0}, 374 {"scr_el3", SCR_EL3, 0}, 375 {"mdcr_el2", MDCR_EL2, 0}, 376 {"sder32_el3", SDER32_EL3, 0}, 377 {"cptr_el2", CPTR_EL2, 0}, 378 {"cptr_el3", CPTR_EL3, 0}, 379 {"hstr_el2", HSTR_EL2, 0}, 380 {"hacr_el2", HACR_EL2, 0}, 381 {"mdcr_el3", MDCR_EL3, 0}, 382 {"ttbr0_el1", TTBR0_EL1, 0}, 383 {"ttbr0_el2", TTBR0_EL2, 0}, 384 {"ttbr0_el3", TTBR0_EL3, 0}, 385 {"ttbr1_el1", TTBR1_EL1, 0}, 386 {"tcr_el1", TCR_EL1, 0}, 387 {"tcr_el2", TCR_EL2, 0}, 388 {"tcr_el3", TCR_EL3, 0}, 389 {"vttbr_el2", VTTBR_EL2, 0}, 390 {"vtcr_el2", VTCR_EL2, 0}, 391 {"dacr32_el2", DACR32_EL2, 0}, 392 {"spsr_el1", SPSR_EL1, 0}, 393 {"spsr_el2", SPSR_EL2, 0}, 394 {"spsr_el3", SPSR_EL3, 0}, 395 {"elr_el1", ELR_EL1, 0}, 396 {"elr_el2", ELR_EL2, 0}, 397 {"elr_el3", ELR_EL3, 0}, 398 {"sp_el0", SP_EL0, 0}, 399 {"sp_el1", SP_EL1, 0}, 400 {"sp_el2", SP_EL2, 0}, 401 {"spsel", SPSel, 0}, 402 {"nzcv", NZCV, 0}, 403 {"daif", DAIF, 0}, 404 {"currentel", CurrentEL, 0}, 405 {"spsr_irq", SPSR_irq, 0}, 406 {"spsr_abt", SPSR_abt, 0}, 407 {"spsr_und", SPSR_und, 0}, 408 {"spsr_fiq", SPSR_fiq, 0}, 409 {"fpcr", FPCR, 0}, 410 {"fpsr", FPSR, 0}, 411 {"dspsr_el0", DSPSR_EL0, 0}, 412 {"dlr_el0", DLR_EL0, 0}, 413 {"ifsr32_el2", IFSR32_EL2, 0}, 414 {"afsr0_el1", AFSR0_EL1, 0}, 415 {"afsr0_el2", AFSR0_EL2, 0}, 416 {"afsr0_el3", AFSR0_EL3, 0}, 417 {"afsr1_el1", AFSR1_EL1, 0}, 418 {"afsr1_el2", AFSR1_EL2, 0}, 419 {"afsr1_el3", AFSR1_EL3, 0}, 420 {"esr_el1", ESR_EL1, 0}, 421 {"esr_el2", ESR_EL2, 0}, 422 {"esr_el3", ESR_EL3, 0}, 423 {"fpexc32_el2", FPEXC32_EL2, 0}, 424 {"far_el1", FAR_EL1, 0}, 425 {"far_el2", FAR_EL2, 0}, 426 {"far_el3", FAR_EL3, 0}, 427 {"hpfar_el2", HPFAR_EL2, 0}, 428 {"par_el1", PAR_EL1, 0}, 429 {"pmcr_el0", PMCR_EL0, 0}, 430 {"pmcntenset_el0", PMCNTENSET_EL0, 0}, 431 {"pmcntenclr_el0", PMCNTENCLR_EL0, 0}, 432 {"pmovsclr_el0", PMOVSCLR_EL0, 0}, 433 {"pmselr_el0", PMSELR_EL0, 0}, 434 {"pmccntr_el0", PMCCNTR_EL0, 0}, 435 {"pmxevtyper_el0", PMXEVTYPER_EL0, 0}, 436 {"pmxevcntr_el0", PMXEVCNTR_EL0, 0}, 437 {"pmuserenr_el0", PMUSERENR_EL0, 0}, 438 {"pmintenset_el1", PMINTENSET_EL1, 0}, 439 {"pmintenclr_el1", PMINTENCLR_EL1, 0}, 440 {"pmovsset_el0", PMOVSSET_EL0, 0}, 441 {"mair_el1", MAIR_EL1, 0}, 442 {"mair_el2", MAIR_EL2, 0}, 443 {"mair_el3", MAIR_EL3, 0}, 444 {"amair_el1", AMAIR_EL1, 0}, 445 {"amair_el2", AMAIR_EL2, 0}, 446 {"amair_el3", AMAIR_EL3, 0}, 447 {"vbar_el1", VBAR_EL1, 0}, 448 {"vbar_el2", VBAR_EL2, 0}, 449 {"vbar_el3", VBAR_EL3, 0}, 450 {"rmr_el1", RMR_EL1, 0}, 451 {"rmr_el2", RMR_EL2, 0}, 452 {"rmr_el3", RMR_EL3, 0}, 453 {"contextidr_el1", CONTEXTIDR_EL1, 0}, 454 {"tpidr_el0", TPIDR_EL0, 0}, 455 {"tpidr_el2", TPIDR_EL2, 0}, 456 {"tpidr_el3", TPIDR_EL3, 0}, 457 {"tpidrro_el0", TPIDRRO_EL0, 0}, 458 {"tpidr_el1", TPIDR_EL1, 0}, 459 {"cntfrq_el0", CNTFRQ_EL0, 0}, 460 {"cntvoff_el2", CNTVOFF_EL2, 0}, 461 {"cntkctl_el1", CNTKCTL_EL1, 0}, 462 {"cnthctl_el2", CNTHCTL_EL2, 0}, 463 {"cntp_tval_el0", CNTP_TVAL_EL0, 0}, 464 {"cnthp_tval_el2", CNTHP_TVAL_EL2, 0}, 465 {"cntps_tval_el1", CNTPS_TVAL_EL1, 0}, 466 {"cntp_ctl_el0", CNTP_CTL_EL0, 0}, 467 {"cnthp_ctl_el2", CNTHP_CTL_EL2, 0}, 468 {"cntps_ctl_el1", CNTPS_CTL_EL1, 0}, 469 {"cntp_cval_el0", CNTP_CVAL_EL0, 0}, 470 {"cnthp_cval_el2", CNTHP_CVAL_EL2, 0}, 471 {"cntps_cval_el1", CNTPS_CVAL_EL1, 0}, 472 {"cntv_tval_el0", CNTV_TVAL_EL0, 0}, 473 {"cntv_ctl_el0", CNTV_CTL_EL0, 0}, 474 {"cntv_cval_el0", CNTV_CVAL_EL0, 0}, 475 {"pmevcntr0_el0", PMEVCNTR0_EL0, 0}, 476 {"pmevcntr1_el0", PMEVCNTR1_EL0, 0}, 477 {"pmevcntr2_el0", PMEVCNTR2_EL0, 0}, 478 {"pmevcntr3_el0", PMEVCNTR3_EL0, 0}, 479 {"pmevcntr4_el0", PMEVCNTR4_EL0, 0}, 480 {"pmevcntr5_el0", PMEVCNTR5_EL0, 0}, 481 {"pmevcntr6_el0", PMEVCNTR6_EL0, 0}, 482 {"pmevcntr7_el0", PMEVCNTR7_EL0, 0}, 483 {"pmevcntr8_el0", PMEVCNTR8_EL0, 0}, 484 {"pmevcntr9_el0", PMEVCNTR9_EL0, 0}, 485 {"pmevcntr10_el0", PMEVCNTR10_EL0, 0}, 486 {"pmevcntr11_el0", PMEVCNTR11_EL0, 0}, 487 {"pmevcntr12_el0", PMEVCNTR12_EL0, 0}, 488 {"pmevcntr13_el0", PMEVCNTR13_EL0, 0}, 489 {"pmevcntr14_el0", PMEVCNTR14_EL0, 0}, 490 {"pmevcntr15_el0", PMEVCNTR15_EL0, 0}, 491 {"pmevcntr16_el0", PMEVCNTR16_EL0, 0}, 492 {"pmevcntr17_el0", PMEVCNTR17_EL0, 0}, 493 {"pmevcntr18_el0", PMEVCNTR18_EL0, 0}, 494 {"pmevcntr19_el0", PMEVCNTR19_EL0, 0}, 495 {"pmevcntr20_el0", PMEVCNTR20_EL0, 0}, 496 {"pmevcntr21_el0", PMEVCNTR21_EL0, 0}, 497 {"pmevcntr22_el0", PMEVCNTR22_EL0, 0}, 498 {"pmevcntr23_el0", PMEVCNTR23_EL0, 0}, 499 {"pmevcntr24_el0", PMEVCNTR24_EL0, 0}, 500 {"pmevcntr25_el0", PMEVCNTR25_EL0, 0}, 501 {"pmevcntr26_el0", PMEVCNTR26_EL0, 0}, 502 {"pmevcntr27_el0", PMEVCNTR27_EL0, 0}, 503 {"pmevcntr28_el0", PMEVCNTR28_EL0, 0}, 504 {"pmevcntr29_el0", PMEVCNTR29_EL0, 0}, 505 {"pmevcntr30_el0", PMEVCNTR30_EL0, 0}, 506 {"pmccfiltr_el0", PMCCFILTR_EL0, 0}, 507 {"pmevtyper0_el0", PMEVTYPER0_EL0, 0}, 508 {"pmevtyper1_el0", PMEVTYPER1_EL0, 0}, 509 {"pmevtyper2_el0", PMEVTYPER2_EL0, 0}, 510 {"pmevtyper3_el0", PMEVTYPER3_EL0, 0}, 511 {"pmevtyper4_el0", PMEVTYPER4_EL0, 0}, 512 {"pmevtyper5_el0", PMEVTYPER5_EL0, 0}, 513 {"pmevtyper6_el0", PMEVTYPER6_EL0, 0}, 514 {"pmevtyper7_el0", PMEVTYPER7_EL0, 0}, 515 {"pmevtyper8_el0", PMEVTYPER8_EL0, 0}, 516 {"pmevtyper9_el0", PMEVTYPER9_EL0, 0}, 517 {"pmevtyper10_el0", PMEVTYPER10_EL0, 0}, 518 {"pmevtyper11_el0", PMEVTYPER11_EL0, 0}, 519 {"pmevtyper12_el0", PMEVTYPER12_EL0, 0}, 520 {"pmevtyper13_el0", PMEVTYPER13_EL0, 0}, 521 {"pmevtyper14_el0", PMEVTYPER14_EL0, 0}, 522 {"pmevtyper15_el0", PMEVTYPER15_EL0, 0}, 523 {"pmevtyper16_el0", PMEVTYPER16_EL0, 0}, 524 {"pmevtyper17_el0", PMEVTYPER17_EL0, 0}, 525 {"pmevtyper18_el0", PMEVTYPER18_EL0, 0}, 526 {"pmevtyper19_el0", PMEVTYPER19_EL0, 0}, 527 {"pmevtyper20_el0", PMEVTYPER20_EL0, 0}, 528 {"pmevtyper21_el0", PMEVTYPER21_EL0, 0}, 529 {"pmevtyper22_el0", PMEVTYPER22_EL0, 0}, 530 {"pmevtyper23_el0", PMEVTYPER23_EL0, 0}, 531 {"pmevtyper24_el0", PMEVTYPER24_EL0, 0}, 532 {"pmevtyper25_el0", PMEVTYPER25_EL0, 0}, 533 {"pmevtyper26_el0", PMEVTYPER26_EL0, 0}, 534 {"pmevtyper27_el0", PMEVTYPER27_EL0, 0}, 535 {"pmevtyper28_el0", PMEVTYPER28_EL0, 0}, 536 {"pmevtyper29_el0", PMEVTYPER29_EL0, 0}, 537 {"pmevtyper30_el0", PMEVTYPER30_EL0, 0}, 538 539 // Trace registers 540 {"trcprgctlr", TRCPRGCTLR, 0}, 541 {"trcprocselr", TRCPROCSELR, 0}, 542 {"trcconfigr", TRCCONFIGR, 0}, 543 {"trcauxctlr", TRCAUXCTLR, 0}, 544 {"trceventctl0r", TRCEVENTCTL0R, 0}, 545 {"trceventctl1r", TRCEVENTCTL1R, 0}, 546 {"trcstallctlr", TRCSTALLCTLR, 0}, 547 {"trctsctlr", TRCTSCTLR, 0}, 548 {"trcsyncpr", TRCSYNCPR, 0}, 549 {"trcccctlr", TRCCCCTLR, 0}, 550 {"trcbbctlr", TRCBBCTLR, 0}, 551 {"trctraceidr", TRCTRACEIDR, 0}, 552 {"trcqctlr", TRCQCTLR, 0}, 553 {"trcvictlr", TRCVICTLR, 0}, 554 {"trcviiectlr", TRCVIIECTLR, 0}, 555 {"trcvissctlr", TRCVISSCTLR, 0}, 556 {"trcvipcssctlr", TRCVIPCSSCTLR, 0}, 557 {"trcvdctlr", TRCVDCTLR, 0}, 558 {"trcvdsacctlr", TRCVDSACCTLR, 0}, 559 {"trcvdarcctlr", TRCVDARCCTLR, 0}, 560 {"trcseqevr0", TRCSEQEVR0, 0}, 561 {"trcseqevr1", TRCSEQEVR1, 0}, 562 {"trcseqevr2", TRCSEQEVR2, 0}, 563 {"trcseqrstevr", TRCSEQRSTEVR, 0}, 564 {"trcseqstr", TRCSEQSTR, 0}, 565 {"trcextinselr", TRCEXTINSELR, 0}, 566 {"trccntrldvr0", TRCCNTRLDVR0, 0}, 567 {"trccntrldvr1", TRCCNTRLDVR1, 0}, 568 {"trccntrldvr2", TRCCNTRLDVR2, 0}, 569 {"trccntrldvr3", TRCCNTRLDVR3, 0}, 570 {"trccntctlr0", TRCCNTCTLR0, 0}, 571 {"trccntctlr1", TRCCNTCTLR1, 0}, 572 {"trccntctlr2", TRCCNTCTLR2, 0}, 573 {"trccntctlr3", TRCCNTCTLR3, 0}, 574 {"trccntvr0", TRCCNTVR0, 0}, 575 {"trccntvr1", TRCCNTVR1, 0}, 576 {"trccntvr2", TRCCNTVR2, 0}, 577 {"trccntvr3", TRCCNTVR3, 0}, 578 {"trcimspec0", TRCIMSPEC0, 0}, 579 {"trcimspec1", TRCIMSPEC1, 0}, 580 {"trcimspec2", TRCIMSPEC2, 0}, 581 {"trcimspec3", TRCIMSPEC3, 0}, 582 {"trcimspec4", TRCIMSPEC4, 0}, 583 {"trcimspec5", TRCIMSPEC5, 0}, 584 {"trcimspec6", TRCIMSPEC6, 0}, 585 {"trcimspec7", TRCIMSPEC7, 0}, 586 {"trcrsctlr2", TRCRSCTLR2, 0}, 587 {"trcrsctlr3", TRCRSCTLR3, 0}, 588 {"trcrsctlr4", TRCRSCTLR4, 0}, 589 {"trcrsctlr5", TRCRSCTLR5, 0}, 590 {"trcrsctlr6", TRCRSCTLR6, 0}, 591 {"trcrsctlr7", TRCRSCTLR7, 0}, 592 {"trcrsctlr8", TRCRSCTLR8, 0}, 593 {"trcrsctlr9", TRCRSCTLR9, 0}, 594 {"trcrsctlr10", TRCRSCTLR10, 0}, 595 {"trcrsctlr11", TRCRSCTLR11, 0}, 596 {"trcrsctlr12", TRCRSCTLR12, 0}, 597 {"trcrsctlr13", TRCRSCTLR13, 0}, 598 {"trcrsctlr14", TRCRSCTLR14, 0}, 599 {"trcrsctlr15", TRCRSCTLR15, 0}, 600 {"trcrsctlr16", TRCRSCTLR16, 0}, 601 {"trcrsctlr17", TRCRSCTLR17, 0}, 602 {"trcrsctlr18", TRCRSCTLR18, 0}, 603 {"trcrsctlr19", TRCRSCTLR19, 0}, 604 {"trcrsctlr20", TRCRSCTLR20, 0}, 605 {"trcrsctlr21", TRCRSCTLR21, 0}, 606 {"trcrsctlr22", TRCRSCTLR22, 0}, 607 {"trcrsctlr23", TRCRSCTLR23, 0}, 608 {"trcrsctlr24", TRCRSCTLR24, 0}, 609 {"trcrsctlr25", TRCRSCTLR25, 0}, 610 {"trcrsctlr26", TRCRSCTLR26, 0}, 611 {"trcrsctlr27", TRCRSCTLR27, 0}, 612 {"trcrsctlr28", TRCRSCTLR28, 0}, 613 {"trcrsctlr29", TRCRSCTLR29, 0}, 614 {"trcrsctlr30", TRCRSCTLR30, 0}, 615 {"trcrsctlr31", TRCRSCTLR31, 0}, 616 {"trcssccr0", TRCSSCCR0, 0}, 617 {"trcssccr1", TRCSSCCR1, 0}, 618 {"trcssccr2", TRCSSCCR2, 0}, 619 {"trcssccr3", TRCSSCCR3, 0}, 620 {"trcssccr4", TRCSSCCR4, 0}, 621 {"trcssccr5", TRCSSCCR5, 0}, 622 {"trcssccr6", TRCSSCCR6, 0}, 623 {"trcssccr7", TRCSSCCR7, 0}, 624 {"trcsscsr0", TRCSSCSR0, 0}, 625 {"trcsscsr1", TRCSSCSR1, 0}, 626 {"trcsscsr2", TRCSSCSR2, 0}, 627 {"trcsscsr3", TRCSSCSR3, 0}, 628 {"trcsscsr4", TRCSSCSR4, 0}, 629 {"trcsscsr5", TRCSSCSR5, 0}, 630 {"trcsscsr6", TRCSSCSR6, 0}, 631 {"trcsscsr7", TRCSSCSR7, 0}, 632 {"trcsspcicr0", TRCSSPCICR0, 0}, 633 {"trcsspcicr1", TRCSSPCICR1, 0}, 634 {"trcsspcicr2", TRCSSPCICR2, 0}, 635 {"trcsspcicr3", TRCSSPCICR3, 0}, 636 {"trcsspcicr4", TRCSSPCICR4, 0}, 637 {"trcsspcicr5", TRCSSPCICR5, 0}, 638 {"trcsspcicr6", TRCSSPCICR6, 0}, 639 {"trcsspcicr7", TRCSSPCICR7, 0}, 640 {"trcpdcr", TRCPDCR, 0}, 641 {"trcacvr0", TRCACVR0, 0}, 642 {"trcacvr1", TRCACVR1, 0}, 643 {"trcacvr2", TRCACVR2, 0}, 644 {"trcacvr3", TRCACVR3, 0}, 645 {"trcacvr4", TRCACVR4, 0}, 646 {"trcacvr5", TRCACVR5, 0}, 647 {"trcacvr6", TRCACVR6, 0}, 648 {"trcacvr7", TRCACVR7, 0}, 649 {"trcacvr8", TRCACVR8, 0}, 650 {"trcacvr9", TRCACVR9, 0}, 651 {"trcacvr10", TRCACVR10, 0}, 652 {"trcacvr11", TRCACVR11, 0}, 653 {"trcacvr12", TRCACVR12, 0}, 654 {"trcacvr13", TRCACVR13, 0}, 655 {"trcacvr14", TRCACVR14, 0}, 656 {"trcacvr15", TRCACVR15, 0}, 657 {"trcacatr0", TRCACATR0, 0}, 658 {"trcacatr1", TRCACATR1, 0}, 659 {"trcacatr2", TRCACATR2, 0}, 660 {"trcacatr3", TRCACATR3, 0}, 661 {"trcacatr4", TRCACATR4, 0}, 662 {"trcacatr5", TRCACATR5, 0}, 663 {"trcacatr6", TRCACATR6, 0}, 664 {"trcacatr7", TRCACATR7, 0}, 665 {"trcacatr8", TRCACATR8, 0}, 666 {"trcacatr9", TRCACATR9, 0}, 667 {"trcacatr10", TRCACATR10, 0}, 668 {"trcacatr11", TRCACATR11, 0}, 669 {"trcacatr12", TRCACATR12, 0}, 670 {"trcacatr13", TRCACATR13, 0}, 671 {"trcacatr14", TRCACATR14, 0}, 672 {"trcacatr15", TRCACATR15, 0}, 673 {"trcdvcvr0", TRCDVCVR0, 0}, 674 {"trcdvcvr1", TRCDVCVR1, 0}, 675 {"trcdvcvr2", TRCDVCVR2, 0}, 676 {"trcdvcvr3", TRCDVCVR3, 0}, 677 {"trcdvcvr4", TRCDVCVR4, 0}, 678 {"trcdvcvr5", TRCDVCVR5, 0}, 679 {"trcdvcvr6", TRCDVCVR6, 0}, 680 {"trcdvcvr7", TRCDVCVR7, 0}, 681 {"trcdvcmr0", TRCDVCMR0, 0}, 682 {"trcdvcmr1", TRCDVCMR1, 0}, 683 {"trcdvcmr2", TRCDVCMR2, 0}, 684 {"trcdvcmr3", TRCDVCMR3, 0}, 685 {"trcdvcmr4", TRCDVCMR4, 0}, 686 {"trcdvcmr5", TRCDVCMR5, 0}, 687 {"trcdvcmr6", TRCDVCMR6, 0}, 688 {"trcdvcmr7", TRCDVCMR7, 0}, 689 {"trccidcvr0", TRCCIDCVR0, 0}, 690 {"trccidcvr1", TRCCIDCVR1, 0}, 691 {"trccidcvr2", TRCCIDCVR2, 0}, 692 {"trccidcvr3", TRCCIDCVR3, 0}, 693 {"trccidcvr4", TRCCIDCVR4, 0}, 694 {"trccidcvr5", TRCCIDCVR5, 0}, 695 {"trccidcvr6", TRCCIDCVR6, 0}, 696 {"trccidcvr7", TRCCIDCVR7, 0}, 697 {"trcvmidcvr0", TRCVMIDCVR0, 0}, 698 {"trcvmidcvr1", TRCVMIDCVR1, 0}, 699 {"trcvmidcvr2", TRCVMIDCVR2, 0}, 700 {"trcvmidcvr3", TRCVMIDCVR3, 0}, 701 {"trcvmidcvr4", TRCVMIDCVR4, 0}, 702 {"trcvmidcvr5", TRCVMIDCVR5, 0}, 703 {"trcvmidcvr6", TRCVMIDCVR6, 0}, 704 {"trcvmidcvr7", TRCVMIDCVR7, 0}, 705 {"trccidcctlr0", TRCCIDCCTLR0, 0}, 706 {"trccidcctlr1", TRCCIDCCTLR1, 0}, 707 {"trcvmidcctlr0", TRCVMIDCCTLR0, 0}, 708 {"trcvmidcctlr1", TRCVMIDCCTLR1, 0}, 709 {"trcitctrl", TRCITCTRL, 0}, 710 {"trcclaimset", TRCCLAIMSET, 0}, 711 {"trcclaimclr", TRCCLAIMCLR, 0}, 712 713 // GICv3 registers 714 {"icc_bpr1_el1", ICC_BPR1_EL1, 0}, 715 {"icc_bpr0_el1", ICC_BPR0_EL1, 0}, 716 {"icc_pmr_el1", ICC_PMR_EL1, 0}, 717 {"icc_ctlr_el1", ICC_CTLR_EL1, 0}, 718 {"icc_ctlr_el3", ICC_CTLR_EL3, 0}, 719 {"icc_sre_el1", ICC_SRE_EL1, 0}, 720 {"icc_sre_el2", ICC_SRE_EL2, 0}, 721 {"icc_sre_el3", ICC_SRE_EL3, 0}, 722 {"icc_igrpen0_el1", ICC_IGRPEN0_EL1, 0}, 723 {"icc_igrpen1_el1", ICC_IGRPEN1_EL1, 0}, 724 {"icc_igrpen1_el3", ICC_IGRPEN1_EL3, 0}, 725 {"icc_seien_el1", ICC_SEIEN_EL1, 0}, 726 {"icc_ap0r0_el1", ICC_AP0R0_EL1, 0}, 727 {"icc_ap0r1_el1", ICC_AP0R1_EL1, 0}, 728 {"icc_ap0r2_el1", ICC_AP0R2_EL1, 0}, 729 {"icc_ap0r3_el1", ICC_AP0R3_EL1, 0}, 730 {"icc_ap1r0_el1", ICC_AP1R0_EL1, 0}, 731 {"icc_ap1r1_el1", ICC_AP1R1_EL1, 0}, 732 {"icc_ap1r2_el1", ICC_AP1R2_EL1, 0}, 733 {"icc_ap1r3_el1", ICC_AP1R3_EL1, 0}, 734 {"ich_ap0r0_el2", ICH_AP0R0_EL2, 0}, 735 {"ich_ap0r1_el2", ICH_AP0R1_EL2, 0}, 736 {"ich_ap0r2_el2", ICH_AP0R2_EL2, 0}, 737 {"ich_ap0r3_el2", ICH_AP0R3_EL2, 0}, 738 {"ich_ap1r0_el2", ICH_AP1R0_EL2, 0}, 739 {"ich_ap1r1_el2", ICH_AP1R1_EL2, 0}, 740 {"ich_ap1r2_el2", ICH_AP1R2_EL2, 0}, 741 {"ich_ap1r3_el2", ICH_AP1R3_EL2, 0}, 742 {"ich_hcr_el2", ICH_HCR_EL2, 0}, 743 {"ich_misr_el2", ICH_MISR_EL2, 0}, 744 {"ich_vmcr_el2", ICH_VMCR_EL2, 0}, 745 {"ich_vseir_el2", ICH_VSEIR_EL2, 0}, 746 {"ich_lr0_el2", ICH_LR0_EL2, 0}, 747 {"ich_lr1_el2", ICH_LR1_EL2, 0}, 748 {"ich_lr2_el2", ICH_LR2_EL2, 0}, 749 {"ich_lr3_el2", ICH_LR3_EL2, 0}, 750 {"ich_lr4_el2", ICH_LR4_EL2, 0}, 751 {"ich_lr5_el2", ICH_LR5_EL2, 0}, 752 {"ich_lr6_el2", ICH_LR6_EL2, 0}, 753 {"ich_lr7_el2", ICH_LR7_EL2, 0}, 754 {"ich_lr8_el2", ICH_LR8_EL2, 0}, 755 {"ich_lr9_el2", ICH_LR9_EL2, 0}, 756 {"ich_lr10_el2", ICH_LR10_EL2, 0}, 757 {"ich_lr11_el2", ICH_LR11_EL2, 0}, 758 {"ich_lr12_el2", ICH_LR12_EL2, 0}, 759 {"ich_lr13_el2", ICH_LR13_EL2, 0}, 760 {"ich_lr14_el2", ICH_LR14_EL2, 0}, 761 {"ich_lr15_el2", ICH_LR15_EL2, 0}, 762 763 // Cyclone registers 764 {"cpm_ioacc_ctl_el3", CPM_IOACC_CTL_EL3, AArch64::ProcCyclone}, 765 766 // v8.1a "Privileged Access Never" extension-specific system registers 767 {"pan", PAN, AArch64::HasV8_1aOps}, 768 769 // v8.1a "Limited Ordering Regions" extension-specific system registers 770 {"lorsa_el1", LORSA_EL1, AArch64::HasV8_1aOps}, 771 {"lorea_el1", LOREA_EL1, AArch64::HasV8_1aOps}, 772 {"lorn_el1", LORN_EL1, AArch64::HasV8_1aOps}, 773 {"lorc_el1", LORC_EL1, AArch64::HasV8_1aOps}, 774 {"lorid_el1", LORID_EL1, AArch64::HasV8_1aOps}, 775 776 // v8.1a "Virtualization host extensions" system registers 777 {"ttbr1_el2", TTBR1_EL2, AArch64::HasV8_1aOps}, 778 {"contextidr_el2", CONTEXTIDR_EL2, AArch64::HasV8_1aOps}, 779 {"cnthv_tval_el2", CNTHV_TVAL_EL2, AArch64::HasV8_1aOps}, 780 {"cnthv_cval_el2", CNTHV_CVAL_EL2, AArch64::HasV8_1aOps}, 781 {"cnthv_ctl_el2", CNTHV_CTL_EL2, AArch64::HasV8_1aOps}, 782 {"sctlr_el12", SCTLR_EL12, AArch64::HasV8_1aOps}, 783 {"cpacr_el12", CPACR_EL12, AArch64::HasV8_1aOps}, 784 {"ttbr0_el12", TTBR0_EL12, AArch64::HasV8_1aOps}, 785 {"ttbr1_el12", TTBR1_EL12, AArch64::HasV8_1aOps}, 786 {"tcr_el12", TCR_EL12, AArch64::HasV8_1aOps}, 787 {"afsr0_el12", AFSR0_EL12, AArch64::HasV8_1aOps}, 788 {"afsr1_el12", AFSR1_EL12, AArch64::HasV8_1aOps}, 789 {"esr_el12", ESR_EL12, AArch64::HasV8_1aOps}, 790 {"far_el12", FAR_EL12, AArch64::HasV8_1aOps}, 791 {"mair_el12", MAIR_EL12, AArch64::HasV8_1aOps}, 792 {"amair_el12", AMAIR_EL12, AArch64::HasV8_1aOps}, 793 {"vbar_el12", VBAR_EL12, AArch64::HasV8_1aOps}, 794 {"contextidr_el12", CONTEXTIDR_EL12, AArch64::HasV8_1aOps}, 795 {"cntkctl_el12", CNTKCTL_EL12, AArch64::HasV8_1aOps}, 796 {"cntp_tval_el02", CNTP_TVAL_EL02, AArch64::HasV8_1aOps}, 797 {"cntp_ctl_el02", CNTP_CTL_EL02, AArch64::HasV8_1aOps}, 798 {"cntp_cval_el02", CNTP_CVAL_EL02, AArch64::HasV8_1aOps}, 799 {"cntv_tval_el02", CNTV_TVAL_EL02, AArch64::HasV8_1aOps}, 800 {"cntv_ctl_el02", CNTV_CTL_EL02, AArch64::HasV8_1aOps}, 801 {"cntv_cval_el02", CNTV_CVAL_EL02, AArch64::HasV8_1aOps}, 802 {"spsr_el12", SPSR_EL12, AArch64::HasV8_1aOps}, 803 {"elr_el12", ELR_EL12, AArch64::HasV8_1aOps}, 804 }; 805 806 uint32_t 807 AArch64SysReg::SysRegMapper::fromString(StringRef Name, uint64_t FeatureBits, 808 bool &Valid) const { 809 std::string NameLower = Name.lower(); 810 811 // First search the registers shared by all 812 for (unsigned i = 0; i < array_lengthof(SysRegMappings); ++i) { 813 if (SysRegMappings[i].isNameEqual(NameLower, FeatureBits)) { 814 Valid = true; 815 return SysRegMappings[i].Value; 816 } 817 } 818 819 // Now try the instruction-specific registers (either read-only or 820 // write-only). 821 for (unsigned i = 0; i < NumInstMappings; ++i) { 822 if (InstMappings[i].isNameEqual(NameLower, FeatureBits)) { 823 Valid = true; 824 return InstMappings[i].Value; 825 } 826 } 827 828 // Try to parse an S<op0>_<op1>_<Cn>_<Cm>_<op2> register name 829 Regex GenericRegPattern("^s([0-3])_([0-7])_c([0-9]|1[0-5])_c([0-9]|1[0-5])_([0-7])$"); 830 831 SmallVector<StringRef, 5> Ops; 832 if (!GenericRegPattern.match(NameLower, &Ops)) { 833 Valid = false; 834 return -1; 835 } 836 837 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; 838 uint32_t Bits; 839 Ops[1].getAsInteger(10, Op0); 840 Ops[2].getAsInteger(10, Op1); 841 Ops[3].getAsInteger(10, CRn); 842 Ops[4].getAsInteger(10, CRm); 843 Ops[5].getAsInteger(10, Op2); 844 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2; 845 846 Valid = true; 847 return Bits; 848 } 849 850 std::string 851 AArch64SysReg::SysRegMapper::toString(uint32_t Bits, uint64_t FeatureBits) const { 852 // First search the registers shared by all 853 for (unsigned i = 0; i < array_lengthof(SysRegMappings); ++i) { 854 if (SysRegMappings[i].isValueEqual(Bits, FeatureBits)) { 855 return SysRegMappings[i].Name; 856 } 857 } 858 859 // Now try the instruction-specific registers (either read-only or 860 // write-only). 861 for (unsigned i = 0; i < NumInstMappings; ++i) { 862 if (InstMappings[i].isValueEqual(Bits, FeatureBits)) { 863 return InstMappings[i].Name; 864 } 865 } 866 867 assert(Bits < 0x10000); 868 uint32_t Op0 = (Bits >> 14) & 0x3; 869 uint32_t Op1 = (Bits >> 11) & 0x7; 870 uint32_t CRn = (Bits >> 7) & 0xf; 871 uint32_t CRm = (Bits >> 3) & 0xf; 872 uint32_t Op2 = Bits & 0x7; 873 874 return "s" + utostr(Op0)+ "_" + utostr(Op1) + "_c" + utostr(CRn) 875 + "_c" + utostr(CRm) + "_" + utostr(Op2); 876 } 877 878 const AArch64NamedImmMapper::Mapping AArch64TLBI::TLBIMapper::TLBIMappings[] = { 879 {"ipas2e1is", IPAS2E1IS, 0}, 880 {"ipas2le1is", IPAS2LE1IS, 0}, 881 {"vmalle1is", VMALLE1IS, 0}, 882 {"alle2is", ALLE2IS, 0}, 883 {"alle3is", ALLE3IS, 0}, 884 {"vae1is", VAE1IS, 0}, 885 {"vae2is", VAE2IS, 0}, 886 {"vae3is", VAE3IS, 0}, 887 {"aside1is", ASIDE1IS, 0}, 888 {"vaae1is", VAAE1IS, 0}, 889 {"alle1is", ALLE1IS, 0}, 890 {"vale1is", VALE1IS, 0}, 891 {"vale2is", VALE2IS, 0}, 892 {"vale3is", VALE3IS, 0}, 893 {"vmalls12e1is", VMALLS12E1IS, 0}, 894 {"vaale1is", VAALE1IS, 0}, 895 {"ipas2e1", IPAS2E1, 0}, 896 {"ipas2le1", IPAS2LE1, 0}, 897 {"vmalle1", VMALLE1, 0}, 898 {"alle2", ALLE2, 0}, 899 {"alle3", ALLE3, 0}, 900 {"vae1", VAE1, 0}, 901 {"vae2", VAE2, 0}, 902 {"vae3", VAE3, 0}, 903 {"aside1", ASIDE1, 0}, 904 {"vaae1", VAAE1, 0}, 905 {"alle1", ALLE1, 0}, 906 {"vale1", VALE1, 0}, 907 {"vale2", VALE2, 0}, 908 {"vale3", VALE3, 0}, 909 {"vmalls12e1", VMALLS12E1, 0}, 910 {"vaale1", VAALE1, 0} 911 }; 912 913 AArch64TLBI::TLBIMapper::TLBIMapper() 914 : AArch64NamedImmMapper(TLBIMappings, 0) {} 915
