/external/llvm/lib/CodeGen/ |
RegisterClassInfo.cpp | 84 unsigned NumRegs = RC->getNumRegs(); 87 RCI.Order.reset(new MCPhysReg[NumRegs]); 116 RCI.NumRegs = N + CSRAlias.size(); 117 assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass"); 130 if (StressRA && RCI.NumRegs > StressRA) 131 RCI.NumRegs = StressRA; 136 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) 144 for (unsigned I = 0; I != RCI.NumRegs; ++I)
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MachineRegisterInfo.cpp | 30 unsigned NumRegs = getTargetRegisterInfo()->getNumRegs(); 33 UsedPhysRegMask.resize(NumRegs); 34 PhysRegUseDefLists.reset(new MachineOperand*[NumRegs]());
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VirtRegMap.cpp | 71 unsigned NumRegs = MF->getRegInfo().getNumVirtRegs(); 72 Virt2PhysMap.resize(NumRegs); 73 Virt2StackSlotMap.resize(NumRegs); 74 Virt2SplitMap.resize(NumRegs);
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LiveVariables.cpp | 426 for (unsigned Reg = 1, NumRegs = TRI->getNumRegs(); Reg != NumRegs; ++Reg) { 563 void LiveVariables::runOnBlock(MachineBasicBlock *MBB, const unsigned NumRegs) { 616 for (unsigned i = 0; i != NumRegs; ++i) 626 const unsigned NumRegs = TRI->getNumRegs(); 627 PhysRegDef.assign(NumRegs, nullptr); 628 PhysRegUse.assign(NumRegs, nullptr); 648 runOnBlock(MBB, NumRegs); 650 PhysRegDef.assign(NumRegs, nullptr); 651 PhysRegUse.assign(NumRegs, nullptr) [all...] |
MachineLICM.cpp | 441 unsigned NumRegs = TRI->getNumRegs(); 442 BitVector PhysRegDefs(NumRegs); // Regs defined once in the loop. 443 BitVector PhysRegClobbers(NumRegs); // Regs defined more than once. 476 BitVector TermRegs(NumRegs); [all...] |
/art/runtime/verifier/ |
register_line.h | 201 size_t NumRegs() const {
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/external/llvm/include/llvm/CodeGen/ |
RegisterClassInfo.h | 29 unsigned NumRegs; 36 : Tag(0), NumRegs(0), ProperSubClass(false), MinCost(0), 40 return makeArrayRef(Order.get(), NumRegs); 87 return get(RC).NumRegs;
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/external/llvm/lib/Target/ARM/ |
ARMSelectionDAGInfo.cpp | 185 unsigned NumRegs = NextEmittedNumMemOps - EmittedNumMemOps; 188 DAG.getConstant(NumRegs, dl, MVT::i32)); 192 DstPtrInfo = DstPtrInfo.getWithOffset(NumRegs * VTSize); 193 SrcPtrInfo = SrcPtrInfo.getWithOffset(NumRegs * VTSize);
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ARMExpandPseudoInsts.cpp | 111 uint8_t NumRegs; // D registers loaded or stored 384 unsigned NumRegs = TableEntry->NumRegs; 395 if (NumRegs > 1 && TableEntry->copyAllListRegs) 397 if (NumRegs > 2 && TableEntry->copyAllListRegs) 399 if (NumRegs > 3 && TableEntry->copyAllListRegs) 449 unsigned NumRegs = TableEntry->NumRegs; 470 if (NumRegs > 1 && TableEntry->copyAllListRegs) 472 if (NumRegs > 2 && TableEntry->copyAllListRegs [all...] |
ARMLoadStoreOptimizer.cpp | 581 unsigned NumRegs = Regs.size(); 582 assert(NumRegs > 1); 611 } else if (Offset == -4 * (int)NumRegs + 4 && haveIBAndDA) { 613 } else if (Offset == -4 * (int)NumRegs && isNotVFP && !isThumb1) { 624 if (NumRegs <= 2) 636 NewBase = Regs[NumRegs-1].first; 757 UpdateBaseRegUses(MBB, InsertBefore, DL, Base, NumRegs, Pred, PredReg); [all...] |
ARMBaseInstrInfo.cpp | [all...] |
ARMISelDAGToDAG.cpp | [all...] |
/external/llvm/lib/Target/WebAssembly/ |
WebAssemblyAsmPrinter.cpp | 141 unsigned NumRegs = TLI.getNumRegisters(F.getContext(), VT); 143 for (unsigned i = 0; i != NumRegs; ++i)
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/external/llvm/lib/CodeGen/SelectionDAG/ |
SelectionDAGBuilder.cpp | 270 unsigned NumRegs = 273 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 274 NumParts = NumRegs; // Silence a compiler warning. 554 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, 559 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 560 NumParts = NumRegs; // Silence a compiler warning. 606 unsigned NumRegs = TLI.getNumRegisters(Context, ValueVT); 608 for (unsigned i = 0; i != NumRegs; ++i) 611 Reg += NumRegs; 636 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT) [all...] |
FunctionLoweringInfo.cpp | 369 unsigned NumRegs = TLI->getNumRegisters(Ty->getContext(), ValueVT); 370 for (unsigned i = 0; i != NumRegs; ++i) {
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LegalizeDAG.cpp | 348 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes; 363 for (unsigned i = 1; i < NumRegs; i++) { 473 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes; 485 for (unsigned i = 1; i < NumRegs; i++) { [all...] |
FastISel.cpp | 296 void FastISel::updateValueMap(const Value *I, unsigned Reg, unsigned NumRegs) { 308 for (unsigned i = 0; i < NumRegs; i++) [all...] |
/external/llvm/lib/Target/Sparc/ |
SparcISelDAGToDAG.cpp | 202 unsigned NumRegs = InlineAsm::getNumOperandRegisters(Flag); 203 if (NumRegs) 220 || NumRegs != 2)
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/external/llvm/lib/Target/AMDGPU/InstPrinter/ |
AMDGPUInstPrinter.cpp | 171 unsigned NumRegs; 175 NumRegs = 1; 178 NumRegs = 1; 181 NumRegs = 2; 184 NumRegs = 2; 187 NumRegs = 4; 190 NumRegs = 4; 193 NumRegs = 3; 196 NumRegs = 8; 199 NumRegs = 8 [all...] |
/external/llvm/include/llvm/MC/ |
MCRegisterInfo.h | 156 unsigned NumRegs; // Number of entries in the array 258 NumRegs = NR; 324 assert(RegNo < NumRegs && 369 return NumRegs; 419 assert(RegNo < NumRegs &&
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/external/llvm/lib/Target/AArch64/InstPrinter/ |
AArch64InstPrinter.cpp | [all...] |
/external/llvm/lib/Target/AArch64/ |
AArch64InstrInfo.cpp | [all...] |
/external/llvm/lib/Target/Hexagon/ |
HexagonSplitDouble.cpp | 215 unsigned NumRegs = MRI->getNumVirtRegs(); 216 BitVector DoubleRegs(NumRegs); 217 for (unsigned i = 0; i < NumRegs; ++i) { 223 BitVector FixedRegs(NumRegs); [all...] |
/external/v8/src/ |
frames.cc | [all...] |
/external/clang/lib/Sema/ |
SemaDeclAttr.cpp | [all...] |