| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyRegisterInfo.cpp | 90 static const unsigned Regs[2][2] = {
95 return Regs[TFI->hasFP(MF)][TT.isArch64Bit()];
|
| /external/llvm/lib/CodeGen/ |
| ExecutionDepsFix.cpp | 648 SmallVector<LiveReg, 4> Regs;
660 for (SmallVectorImpl<LiveReg>::iterator i = Regs.begin(), e = Regs.end();
664 Regs.insert(i, LR);
668 Regs.push_back(LR);
674 while (!Regs.empty()) {
676 dv = Regs.pop_back_val().Value;
683 DomainValue *Latest = Regs.pop_back_val().Value;
|
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.cpp | 235 const StringMap<CodeGenRegister*> &Regs = getRegBank().getRegistersByName();
236 StringMap<CodeGenRegister*>::const_iterator I = Regs.find(Name);
237 if (I == Regs.end())
|
| RegisterInfoEmitter.cpp | 56 void EmitRegMapping(raw_ostream &o, const std::deque<CodeGenRegister> &Regs,
59 const std::deque<CodeGenRegister> &Regs,
76 assert(Registers.size() <= 0xffff && "Too many regs to fit in tables");
183 const CodeGenRegister::Vec &Regs = RC.getMembers();
184 if (Regs.empty())
189 OS << " {" << (*Regs.begin())->getWeight(RegBank)
321 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) {
328 for (auto &RE : Regs) {
347 std::string Namespace = Regs.front().TheDef->getValueAsString("Namespace");
395 for (auto &RE : Regs) {
[all...] |
| CodeGenRegisters.cpp | 160 RegUnitIterator(const CodeGenRegister::Vec &Regs):
161 RegI(Regs.begin()), RegE(Regs.end()), UnitI(), UnitE() {
344 // SR is composed of multiple sub-regs. Find their names in this register.
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGBuilder.h | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMLoadStoreOptimizer.cpp | 140 DebugLoc DL, ArrayRef<std::pair<unsigned, bool>> Regs);
144 DebugLoc DL, ArrayRef<std::pair<unsigned, bool>> Regs) const;
534 /// Return the first register of class \p RegClass that is not in \p Regs.
566 static bool ContainsReg(const ArrayRef<std::pair<unsigned, bool>> &Regs,
568 for (const std::pair<unsigned, bool> &R : Regs)
575 /// Regs as the register operands that would be loaded / stored. It returns
580 DebugLoc DL, ArrayRef<std::pair<unsigned, bool>> Regs) {
581 unsigned NumRegs = Regs.size();
595 if (isThumb1 && isi32Load(Opcode) && ContainsReg(Regs, Base)) {
636 NewBase = Regs[NumRegs-1].first
[all...] |
| ARMFrameLowering.cpp | [all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelDAGToDAG.cpp | 668 SDValue Regs[2];
669 if (selectBDXAddr12Only(Addr, Regs[0], Disp, Regs[1]) &&
670 Regs[0].getNode() && Regs[1].getNode()) {
672 Base = Regs[I];
673 Index = Regs[1 - I];
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SIISelLowering.cpp | 739 SmallVector<SDValue, 4> Regs;
740 Regs.push_back(Val);
746 Regs.push_back(Copy);
751 Regs.append(NumElements, DAG.getUNDEF(VT));
753 InVals.push_back(DAG.getNode(ISD::BUILD_VECTOR, DL, Arg.VT, Regs));
[all...] |
| /toolchain/binutils/binutils-2.25/include/opcode/ |
| m88k.h | 65 #define REGs 32
90 /* Not applicable, instruction doesn't write to regs. */
208 Regs[REGs],
210 time_left[REGs],
212 wb_pri[REGs],
213 /* Integer unit control regs. */
214 SFU0_regs[REGs],
215 /* Floating point control regs. */
216 SFU1_regs[REGs],
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| LoopStrengthReduce.cpp | 899 SmallPtrSetImpl<const SCEV *> &Regs,
912 SmallPtrSetImpl<const SCEV *> &Regs,
916 SmallPtrSetImpl<const SCEV *> &Regs,
926 SmallPtrSetImpl<const SCEV *> &Regs,
[all...] |
| /external/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | [all...] |
