| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/ |
| simd.d | 49 [ ]*[a-f0-9]+: f3 0f 5a 00 cvtss2sd \(%eax\),%xmm0
142 [ ]*[a-f0-9]+: f3 0f 5a 00 cvtss2sd \(%eax\),%xmm0
|
| x86-64-simd-intel.d | 68 [ ]*[a-f0-9]+: f3 0f 5a 00 cvtss2sd xmm0,DWORD PTR \[rax\]
187 [ ]*[a-f0-9]+: f3 0f 5a 00 cvtss2sd xmm0,DWORD PTR \[rax\]
|
| x86-64-simd-suffix.d | 68 [ ]*[a-f0-9]+: f3 0f 5a 00 cvtss2sd \(%rax\),%xmm0
187 [ ]*[a-f0-9]+: f3 0f 5a 00 cvtss2sd \(%rax\),%xmm0
|
| x86-64-simd.d | 67 [ ]*[a-f0-9]+: f3 0f 5a 00 cvtss2sd \(%rax\),%xmm0
186 [ ]*[a-f0-9]+: f3 0f 5a 00 cvtss2sd \(%rax\),%xmm0
|
| sse2.d | 138 [ ]*[a-f0-9]+: f3 0f 5a c8 cvtss2sd %xmm0,%xmm1
|
| /external/llvm/test/CodeGen/X86/ |
| sse2-intrinsics-x86.ll | 163 ; CHECK: cvtss2sd
164 %res = call <2 x double> @llvm.x86.sse2.cvtss2sd(<2 x double> %a0, <4 x float> %a1) ; <<2 x double>> [#uses=1]
167 declare <2 x double> @llvm.x86.sse2.cvtss2sd(<2 x double>, <4 x float>) nounwind readnone
|
| stack-folding-fp-sse42.ll | 404 ;CHECK: cvtss2sd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 4-byte Folded Reload
412 ;CHECK: cvtss2sd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
414 %2 = call <2 x double> @llvm.x86.sse2.cvtss2sd(<2 x double> <double 0x0, double 0x0>, <4 x float> %a0)
417 declare <2 x double> @llvm.x86.sse2.cvtss2sd(<2 x double>, <4 x float>) nounwind readnone
[all...] |
| /external/valgrind/memcheck/tests/amd64/ |
| sse_memory.c | 286 TEST_INSN( &AllMask, SS,cvtss2sd) /* reads SS */
|
| /art/compiler/utils/x86_64/ |
| assembler_x86_64.h | 436 void cvtss2sd(XmmRegister dst, XmmRegister src);
437 void cvtss2sd(XmmRegister dst, const Address& src);
[all...] |
| assembler_x86_64.cc | 753 void X86_64Assembler::cvtss2sd(XmmRegister dst, XmmRegister src) { function in class:art::x86_64::X86_64Assembler
763 void X86_64Assembler::cvtss2sd(XmmRegister dst, const Address& src) { function in class:art::x86_64::X86_64Assembler
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/ilp32/ |
| x86-64-simd-intel.d | 68 [ ]*[a-f0-9]+: f3 0f 5a 00 cvtss2sd xmm0,DWORD PTR \[rax\]
187 [ ]*[a-f0-9]+: f3 0f 5a 00 cvtss2sd xmm0,DWORD PTR \[rax\]
|
| x86-64-simd-suffix.d | 68 [ ]*[a-f0-9]+: f3 0f 5a 00 cvtss2sd \(%rax\),%xmm0
187 [ ]*[a-f0-9]+: f3 0f 5a 00 cvtss2sd \(%rax\),%xmm0
|
| x86-64-simd.d | 68 [ ]*[a-f0-9]+: f3 0f 5a 00 cvtss2sd \(%rax\),%xmm0
187 [ ]*[a-f0-9]+: f3 0f 5a 00 cvtss2sd \(%rax\),%xmm0
|
| /external/v8/src/ia32/ |
| assembler-ia32.h | [all...] |
| /art/compiler/utils/x86/ |
| assembler_x86.h | 415 void cvtss2sd(XmmRegister dst, XmmRegister src);
|
| /external/v8/src/x64/ |
| macro-assembler-x64.h | [all...] |
| macro-assembler-x64.cc | 762 void MacroAssembler::Cvtss2sd(XMMRegister dst, XMMRegister src) {
767 cvtss2sd(dst, src);
772 void MacroAssembler::Cvtss2sd(XMMRegister dst, const Operand& src) {
777 cvtss2sd(dst, src);
[all...] |
| assembler-x64.cc | 3236 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) { function in class:v8::internal::Assembler
3247 void Assembler::cvtss2sd(XMMRegister dst, const Operand& src) { function in class:v8::internal::Assembler
[all...] |
| /external/valgrind/none/tests/amd64/ |
| insn_sse2.def | 69 cvtss2sd xmm.ps[12.34,3.33,4.44,5.55] xmm.pd[1.11,2.22] => 1.pd[12.34,2.22]
70 cvtss2sd m128.ps[12.34,3.33,4.44,5.55] xmm.pd[1.11,2.22] => 1.pd[12.34,2.22]
[all...] |
| /external/valgrind/none/tests/x86/ |
| insn_sse2.def | 69 cvtss2sd xmm.ps[12.34,3.33,4.44,5.55] xmm.pd[1.11,2.22] => 1.pd[12.34,2.22]
70 cvtss2sd m128.ps[12.34,3.33,4.44,5.55] xmm.pd[1.11,2.22] => 1.pd[12.34,2.22]
[all...] |
| /external/llvm/lib/Target/X86/ |
| README.txt | 514 cvtss2sd LCPI1_0(%rip), %xmm2
515 cvtss2sd LCPI1_1(%rip), %xmm3
1014 cvtss2sd LCPI1_0, %xmm1
[all...] |
| X86ISelLowering.h | 864 // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
[all...] |
| /external/llvm/test/MC/X86/ |
| x86-32-coverage.s | [all...] |
| /external/elfutils/tests/ |
| testfile44.expect.bz2 | |
| /art/disassembler/ |
| disassembler_x86.cc | 666 opcode1 = "cvtss2sd";
[all...] |
