| /external/llvm/test/CodeGen/Mips/Fast-ISel/ |
| sel1.ll | 11 ; CHECK-NEXT: andi $[[T2:[0-9]+]], $[[T1]], 1
28 ; CHECK-NEXT: andi $[[T4:[0-9]+]], $[[T3]], 1
45 ; CHECK-NEXT: andi $[[T4:[0-9]+]], $[[T3]], 1
60 ; CHECK-NEXT: andi $[[T2:[0-9]+]], $[[T1]], 1
76 ; CHECK-NEXT: andi $[[T2:[0-9]+]], $[[T1]], 1
92 ; CHECK-NEXT: andi $[[T2:[0-9]+]], $[[T1]], 1
|
| bswap1.ll | 25 ; 32R1: andi $[[TMP4:[0-9]+]], $[[TMP3]], 65535
43 ; 32R1: andi $[[TMP3:[0-9]+]], $[[TMP1]], 65280
45 ; 32R1: andi $[[TMP5:[0-9]+]], $[[B_VAL]], 65280
|
| icmpa.ll | 28 ; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1
49 ; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1
69 ; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1
89 ; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1
109 ; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1
129 ; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1
148 ; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1
167 ; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1
188 ; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1
207 ; CHECK: andi ${{[0-9]+}}, $[[REG2]],
[all...] |
| loadstoreconv.ll | 40 ; CHECK: andi $[[REG2:[0-9]+]], $[[REG1]], 1
60 ; CHECK: andi ${{[0-9]+}}, $[[REG1]], 255
102 ; CHECK: andi ${{[0-9]+}}, $[[REG1]], 65535
138 ; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1
152 ; CHECK: andi ${{[0-9]+}}, $[[REG1]], 255
|
| /external/llvm/test/CodeGen/Mips/ |
| fcmp.ll | 38 ; 32-CMP-DAG: andi $2, $[[T1]], 1
42 ; 64-CMP-DAG: andi $2, $[[T1]], 1
62 ; 32-CMP-DAG: andi $2, $[[T1]], 1
66 ; 64-CMP-DAG: andi $2, $[[T1]], 1
86 ; 32-CMP-DAG: andi $2, $[[T1]], 1
90 ; 64-CMP-DAG: andi $2, $[[T1]], 1
110 ; 32-CMP-DAG: andi $2, $[[T1]], 1
114 ; 64-CMP-DAG: andi $2, $[[T1]], 1
134 ; 32-CMP-DAG: andi $2, $[[T1]], 1
138 ; 64-CMP-DAG: andi $2, $[[T1]],
[all...] |
| micromips-andi.ll | 25 ; CHECK: andi ${{[0-9]+}}, ${{[0-9]+}}
|
| /external/llvm/test/CodeGen/Mips/llvm-ir/ |
| lshr.ll | 56 ; ALL: andi $2, $[[T0]], 255
67 ; ALL: andi $2, $[[T0]], 65535
88 ; M2: andi $[[T1:[0-9]+]], $7, 32
110 ; 32R1-R5: andi $[[T5:[0-9]+]], $7, 32
120 ; 32R6: andi $[[T5:[0-9]+]], $7, 32
142 ; M3: andi $[[T2:[0-9]+]], $[[T0]], 64
165 ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T2]], 64
176 ; 64R6: andi $[[T6:[0-9]+]], $[[T2]], 64
|
| select.ll | 37 ; M2-M3: andi $[[T0:[0-9]+]], $4, 1
45 ; CMOV: andi $[[T0:[0-9]+]], $4, 1
49 ; SEL: andi $[[T0:[0-9]+]], $4, 1
62 ; M2-M3: andi $[[T0:[0-9]+]], $4, 1
70 ; CMOV: andi $[[T0:[0-9]+]], $4, 1
74 ; SEL: andi $[[T0:[0-9]+]], $4, 1
87 ; M2-M3: andi $[[T0:[0-9]+]], $4, 1
95 ; CMOV: andi $[[T0:[0-9]+]], $4, 1
99 ; SEL: andi $[[T0:[0-9]+]], $4, 1
112 ; M2: andi $[[T0:[0-9]+]], $4,
[all...] |
| ashr.ll | 55 ; FIXME: The andi instruction is redundant.
56 ; ALL: andi $[[T0:[0-9]+]], $5, 255
67 ; FIXME: The andi instruction is redundant.
68 ; ALL: andi $[[T0:[0-9]+]], $5, 65535
90 ; M2: andi $[[T1:[0-9]+]], $7, 32
112 ; 32R1-R5: andi $[[T5:[0-9]+]], $7, 32
119 ; 32R6: andi $[[T1:[0-9]+]], $7, 32
148 ; M3: andi $[[T2:[0-9]+]], $[[T0]], 64
171 ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T2]], 64
179 ; 64R6: andi $[[T2:[0-9]+]], $[[T1]], 6
[all...] |
| shl.ll | 55 ; NOT-R2-R6: andi $[[T0:[0-9]+]], $5, 255
60 ; R2-R6: andi $[[T0:[0-9]+]], $5, 255
72 ; NOT-R2-R6: andi $[[T0:[0-9]+]], $5, 65535
77 ; R2-R6: andi $[[T0:[0-9]+]], $5, 65535
100 ; M2: andi $[[T1:[0-9]+]], $7, 32
122 ; 32R1-R5: andi $[[T5:[0-9]+]], $7, 32
132 ; 32R6: andi $[[T5:[0-9]+]], $7, 32
154 ; M3: andi $[[T2:[0-9]+]], $[[T0]], 64
177 ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T2]], 64
188 ; 64R6: andi $[[T6:[0-9]+]], $[[T2]], 6
[all...] |
| /frameworks/native/opengl/libagl/arch-mips/ |
| fixed_asm.S | 36 andi $t1,$t1,0xff /* get the e */
46 andi $t4,$v0,0x1
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/nds32/ |
| to-16bit-v1.s | 26 andi $r0, $r0, 1
27 andi $r7, $r7, 0x7ff
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/tilegx/ |
| t_insns.s | 203 { bnezt r15, target ; andi r5, r6, 5 }
274 { add r15, r16, r17 ; andi r5, r6, 5 ; ld2u r25, r26 }
284 { add r15, r16, r17 ; ld1s r25, r26 ; andi r5, r6, 5 }
336 { add r5, r6, r7 ; andi r15, r16, 5 ; st1 r25, r26 }
383 { addi r15, r16, 5 ; andi r5, r6, 5 ; ld2u r25, r26 }
393 { addi r15, r16, 5 ; ld1s r25, r26 ; andi r5, r6, 5 }
445 { addi r5, r6, 5 ; andi r15, r16, 5 ; st1 r25, r26 }
503 { addx r15, r16, r17 ; andi r5, r6, 5 ; prefetch_l1 r25 }
536 { addx r15, r16, r17 ; prefetch_l2 r25 ; andi r5, r6, 5 }
612 { addxi r15, r16, 5 ; andi r5, r6, 5 ; prefetch_l1 r25
[all...] |
| /art/runtime/interpreter/mterp/mips/ |
| op_shl_long.S | 19 andi v1, a2, 0x20 # shift< shift & 0x20
|
| op_shl_long_2addr.S | 15 andi v1, a2, 0x20 # shift< shift & 0x20
|
| op_shr_long.S | 18 andi v0, a2, 0x20 # shift & 0x20
|
| op_shr_long_2addr.S | 14 andi v0, a2, 0x20 # shift & 0x20
|
| op_ushr_long.S | 19 andi v0, a2, 0x20 # shift & 0x20
|
| op_ushr_long_2addr.S | 15 andi v0, a2, 0x20 # shift & 0x20
|
| /external/llvm/test/MC/Disassembler/Mips/msa/ |
| test_i8.txt | 3 0x78 0x30 0xe8 0x80 # CHECK: andi.b $w2, $w29, 48
|
| /prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.11-4.8/sysroot/usr/include/linux/ |
| mempolicy.h | 8 * Copyright 2003,2004 Andi Kleen SuSE Labs
|
| /external/llvm/test/CodeGen/PowerPC/ |
| crbits.ll | 93 ; CHECK-DAG: andi. {{[0-9]+}}, [[REG1]], 1
108 ; CHECK-DAG: andi. {{[0-9]+}}, 3, 1
111 ; CHECK-DAG: andi. {{[0-9]+}}, 4, 1
126 ; CHECK: andi. {{[0-9]+}}, 3, 1
167 ; CHECK: andi. {{[0-9]+}}, 3, 1
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/tilepro/ |
| t_insns.s | 367 { add r15, r16, r17 ; lh_u r25, r26 ; andi r5, r6, 5 }
390 { add r15, r16, r17 ; sb r25, r26 ; andi r5, r6, 5 }
413 { add r5, r6, r7 ; andi r15, r16, 5 ; sh r25, r26 }
513 { addi r15, r16, 5 ; andi r5, r6, 5 ; lh_u r25, r26 }
594 { addi r5, r6, 5 ; sb r25, r26 ; andi r15, r16, 5 }
759 { and r5, r6, r7 ; andi r15, r16, 5 ; prefetch r25 }
777 { and r5, r6, r7 ; prefetch r25 ; andi r15, r16, 5 }
[all...] |
| /external/valgrind/memcheck/tests/ |
| atomic_incs.c | 59 "andi. %0,%0,1" "\n"
76 "andi. %0,%0,1" "\n"
93 "andi. %0,%0,1" "\n"
159 "andi $t2, $t2, 0xFF" "\n\t" // n = n and 0xFF
165 "andi $t3, $t3, 0xFF" "\n\t" // $t3 = $t3 and 0xFF
203 "andi $t2, $t2, 0xFF" "\n\t" // n = n and 0xFF
209 "andi $t3, $t3, 0xFF" "\n\t" // $t3 = $t3 and 0xFF
289 "andi. %0,%0,1" "\n"
306 "andi. %0,%0,1" "\n"
323 "andi. %0,%0,1" "\n
[all...] |
| /external/llvm/test/MC/PowerPC/ |
| ppc64-operands.s | 151 # CHECK-BE: andi. 0, 3, 32767 # encoding: [0x70,0x60,0x7f,0xff]
152 # CHECK-LE: andi. 0, 3, 32767 # encoding: [0xff,0x7f,0x60,0x70]
153 andi. %r0,%r3,~0x8000@l
155 # CHECK-BE: andi. 0, 3, 0 # encoding: [0x70,0x60,0x00,0x00]
156 # CHECK-LE: andi. 0, 3, 0 # encoding: [0x00,0x00,0x60,0x70]
157 andi. %r0,%r3,!0x8000@l
|
