| /external/llvm/lib/CodeGen/ |
| TwoAddressInstructionPass.cpp | 476 for (unsigned i = 0, NumOps = MI.getNumOperands(); i != NumOps; ++i) {
[all...] |
| MachineVerifier.cpp | 765 unsigned NumOps;
766 for (unsigned e = MI->getNumOperands(); OpNo < e; OpNo += NumOps) {
771 NumOps = 1 + InlineAsm::getNumOperandRegisters(MO.getImm());
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGRRList.cpp | [all...] |
| LegalizeVectorTypes.cpp | [all...] |
| LegalizeDAG.cpp | 114 unsigned NumOps, bool isSigned, SDLoc dl);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMConstantIslandPass.cpp | 624 unsigned NumOps = MI->getDesc().getNumOperands();
626 MI->getOperand(NumOps - (MI->isPredicable() ? 2 : 1));
[all...] |
| ARMBaseInstrInfo.cpp | 159 unsigned NumOps = MCID.getNumOperands();
163 const MachineOperand &Offset = MI->getOperand(NumOps-3);
167 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
168 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
[all...] |
| ARMISelDAGToDAG.cpp | [all...] |
| ARMAsmPrinter.cpp | [all...] |
| ARMLoadStoreOptimizer.cpp | [all...] |
| /toolchain/binutils/binutils-2.25/gas/config/ |
| tc-tic30.c | 1583 unsigned int numops = insn.tm->operands; local
[all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | 571 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
573 for (unsigned i = 0; i < NumOps; ++i, ++I) {
636 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
638 for (unsigned i = 0; i < NumOps; ++i, ++I) {
674 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
675 for (unsigned i = 0; i < NumOps; ++i, ++I) {
[all...] |
| /external/llvm/include/llvm/IR/ |
| Constants.h | [all...] |
| Metadata.h | 756 void *operator new(size_t Size, unsigned NumOps);
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetSelectionDAG.td | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
| HexagonInstrInfo.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| SelectionDAGNodes.h | [all...] |
| MachineRegisterInfo.h | 201 void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | [all...] |
| /external/llvm/lib/IR/ |
| AsmWriter.cpp | [all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| Reassociate.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
| /external/llvm/docs/ |
| BitCodeFormat.rst | 243 [UNABBREV_RECORD, code\ :sub:`vbr6`, numops\ :sub:`vbr6`, op0\ :sub:`vbr6`, op1\ :sub:`vbr6`, ...]
[all...] |
