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      1 //===-- HexagonMCTargetDesc.h - Hexagon Target Descriptions -----*- C++ -*-===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file provides Hexagon specific target descriptions.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H
     15 #define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H
     16 
     17 #include <cstdint>
     18 
     19 #include "llvm/Support/CommandLine.h"
     20 
     21 namespace llvm {
     22 struct InstrItinerary;
     23 struct InstrStage;
     24 class MCAsmBackend;
     25 class MCCodeEmitter;
     26 class MCContext;
     27 class MCInstrInfo;
     28 class MCObjectWriter;
     29 class MCRegisterInfo;
     30 class MCSubtargetInfo;
     31 class Target;
     32 class Triple;
     33 class StringRef;
     34 class raw_ostream;
     35 class raw_pwrite_stream;
     36 
     37 extern Target TheHexagonTarget;
     38 extern cl::opt<bool> HexagonDisableCompound;
     39 extern cl::opt<bool> HexagonDisableDuplex;
     40 extern const InstrStage HexagonStages[];
     41 
     42 MCInstrInfo *createHexagonMCInstrInfo();
     43 
     44 MCCodeEmitter *createHexagonMCCodeEmitter(const MCInstrInfo &MCII,
     45                                           const MCRegisterInfo &MRI,
     46                                           MCContext &MCT);
     47 
     48 MCAsmBackend *createHexagonAsmBackend(const Target &T,
     49                                       const MCRegisterInfo &MRI,
     50                                       const Triple &TT, StringRef CPU);
     51 
     52 MCObjectWriter *createHexagonELFObjectWriter(raw_pwrite_stream &OS,
     53                                              uint8_t OSABI, StringRef CPU);
     54 
     55 namespace HEXAGON_MC {
     56   StringRef selectHexagonCPU(const Triple &TT, StringRef CPU);
     57 }
     58 
     59 } // End llvm namespace
     60 
     61 // Define symbolic names for Hexagon registers.  This defines a mapping from
     62 // register name to register number.
     63 //
     64 #define GET_REGINFO_ENUM
     65 #include "HexagonGenRegisterInfo.inc"
     66 
     67 // Defines symbolic names for the Hexagon instructions.
     68 //
     69 #define GET_INSTRINFO_ENUM
     70 #include "HexagonGenInstrInfo.inc"
     71 
     72 #define GET_SUBTARGETINFO_ENUM
     73 #include "HexagonGenSubtargetInfo.inc"
     74 
     75 #endif
     76