Home | History | Annotate | Download | only in radeon 
      1 //===-- SIInstrFormats.td - SI Instruction Formats ------------------------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // SI Instruction format definitions.
     11 //
     12 // Instructions with _32 take 32-bit operands.
     13 // Instructions with _64 take 64-bit operands.
     14 //
     15 // VOP_* instructions can use either a 32-bit or 64-bit encoding.  The 32-bit
     16 // encoding is the standard encoding, but instruction that make use of
     17 // any of the instruction modifiers must use the 64-bit encoding.
     18 //
     19 // Instructions with _e32 use the 32-bit encoding.
     20 // Instructions with _e64 use the 64-bit encoding.
     21 //
     22 //===----------------------------------------------------------------------===//
     23 
     24 
     25 class VOP3_32 <bits<9> op, string opName, list<dag> pattern>
     26   : VOP3 <op, (outs VReg_32:$dst), (ins AllReg_32:$src0, AllReg_32:$src1, AllReg_32:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5, i32imm:$src6), opName, pattern>;
     27 
     28 class VOP3_64 <bits<9> op, string opName, list<dag> pattern>
     29   : VOP3 <op, (outs VReg_64:$dst), (ins AllReg_64:$src0, AllReg_64:$src1, AllReg_64:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5, i32imm:$src6), opName, pattern>;
     30 
     31 
     32 class SOP1_32 <bits<8> op, string opName, list<dag> pattern>
     33   : SOP1 <op, (outs SReg_32:$dst), (ins SReg_32:$src0), opName, pattern>;
     34 
     35 class SOP1_64 <bits<8> op, string opName, list<dag> pattern>
     36   : SOP1 <op, (outs SReg_64:$dst), (ins SReg_64:$src0), opName, pattern>;
     37 
     38 class SOP2_32 <bits<7> op, string opName, list<dag> pattern>
     39   : SOP2 <op, (outs SReg_32:$dst), (ins SReg_32:$src0, SReg_32:$src1), opName, pattern>;
     40 
     41 class SOP2_64 <bits<7> op, string opName, list<dag> pattern>
     42   : SOP2 <op, (outs SReg_64:$dst), (ins SReg_64:$src0, SReg_64:$src1), opName, pattern>;
     43 
     44 class SOP2_VCC <bits<7> op, string opName, list<dag> pattern>
     45   : SOP2 <op, (outs VCCReg:$vcc), (ins SReg_64:$src0, SReg_64:$src1), opName, pattern>;
     46 
     47 class VOP1_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc,
     48                    string opName, list<dag> pattern> : 
     49   VOP1 <
     50     op, (outs vrc:$dst), (ins arc:$src0), opName, pattern
     51   >;
     52 
     53 multiclass VOP1_32 <bits<8> op, string opName, list<dag> pattern> {
     54   def _e32: VOP1_Helper <op, VReg_32, AllReg_32, opName, pattern>;
     55   def _e64 : VOP3_32 <{1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
     56                       opName, []
     57   >;
     58 }
     59 
     60 multiclass VOP1_64 <bits<8> op, string opName, list<dag> pattern> {
     61 
     62   def _e32 : VOP1_Helper <op, VReg_64, AllReg_64, opName, pattern>;
     63 
     64   def _e64 : VOP3_64 <
     65     {1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
     66     opName, []
     67   >;
     68 }
     69 
     70 class VOP2_Helper <bits<6> op, RegisterClass vrc, RegisterClass arc,
     71                    string opName, list<dag> pattern> :
     72   VOP2 <
     73     op, (outs vrc:$dst), (ins arc:$src0, vrc:$src1), opName, pattern
     74   >;
     75 
     76 multiclass VOP2_32 <bits<6> op, string opName, list<dag> pattern> {
     77 
     78   def _e32 : VOP2_Helper <op, VReg_32, AllReg_32, opName, pattern>;
     79 
     80   def _e64 : VOP3_32 <{1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
     81                       opName, []
     82   >;
     83 }
     84 
     85 multiclass VOP2_64 <bits<6> op, string opName, list<dag> pattern> {
     86   def _e32: VOP2_Helper <op, VReg_64, AllReg_64, opName, pattern>;
     87 
     88   def _e64 : VOP3_64 <
     89     {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
     90     opName, []
     91   >;
     92 }
     93 
     94 class SOPK_32 <bits<5> op, string opName, list<dag> pattern>
     95   : SOPK <op, (outs SReg_32:$dst), (ins i16imm:$src0), opName, pattern>;
     96 
     97 class SOPK_64 <bits<5> op, string opName, list<dag> pattern>
     98   : SOPK <op, (outs SReg_64:$dst), (ins i16imm:$src0), opName, pattern>;
     99 
    100 class VOPC_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc,
    101                  string opName, list<dag> pattern> :
    102   VOPC <
    103     op, (ins arc:$src0, vrc:$src1), opName, pattern
    104   >;
    105 
    106 multiclass VOPC_32 <bits<8> op, string opName, list<dag> pattern> {
    107 
    108   def _e32 : VOPC_Helper <op, VReg_32, AllReg_32, opName, pattern>;
    109 
    110   def _e64 : VOP3_32 <
    111     {0, op{7}, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
    112     opName, []
    113   >;
    114 }
    115 
    116 multiclass VOPC_64 <bits<8> op, string opName, list<dag> pattern> {
    117 
    118   def _e32 : VOPC_Helper <op, VReg_64, AllReg_64, opName, pattern>;
    119 
    120   def _e64 : VOP3_64 <
    121     {0, op{7}, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
    122     opName, []
    123   >;
    124 }
    125 
    126 class SOPC_32 <bits<7> op, string opName, list<dag> pattern>
    127   : SOPC <op, (outs SCCReg:$dst), (ins SReg_32:$src0, SReg_32:$src1), opName, pattern>;
    128 
    129 class SOPC_64 <bits<7> op, string opName, list<dag> pattern>
    130   : SOPC <op, (outs SCCReg:$dst), (ins SReg_64:$src0, SReg_64:$src1), opName, pattern>;
    131 
    132