1 #ifndef _UAPI_MSM_MDP_H_ 2 #define _UAPI_MSM_MDP_H_ 3 4 #include <linux/types.h> 5 #include <linux/fb.h> 6 7 #define MSMFB_IOCTL_MAGIC 'm' 8 #define MSMFB_GRP_DISP _IOW(MSMFB_IOCTL_MAGIC, 1, unsigned int) 9 #define MSMFB_BLIT _IOW(MSMFB_IOCTL_MAGIC, 2, unsigned int) 10 #define MSMFB_SUSPEND_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 128, unsigned int) 11 #define MSMFB_RESUME_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 129, unsigned int) 12 #define MSMFB_CURSOR _IOW(MSMFB_IOCTL_MAGIC, 130, struct fb_cursor) 13 #define MSMFB_SET_LUT _IOW(MSMFB_IOCTL_MAGIC, 131, struct fb_cmap) 14 #define MSMFB_HISTOGRAM _IOWR(MSMFB_IOCTL_MAGIC, 132, struct mdp_histogram_data) 15 /* new ioctls's for set/get ccs matrix */ 16 #define MSMFB_GET_CCS_MATRIX _IOWR(MSMFB_IOCTL_MAGIC, 133, struct mdp_ccs) 17 #define MSMFB_SET_CCS_MATRIX _IOW(MSMFB_IOCTL_MAGIC, 134, struct mdp_ccs) 18 #define MSMFB_OVERLAY_SET _IOWR(MSMFB_IOCTL_MAGIC, 135, \ 19 struct mdp_overlay) 20 #define MSMFB_OVERLAY_UNSET _IOW(MSMFB_IOCTL_MAGIC, 136, unsigned int) 21 22 #define MSMFB_OVERLAY_PLAY _IOW(MSMFB_IOCTL_MAGIC, 137, \ 23 struct msmfb_overlay_data) 24 #define MSMFB_OVERLAY_QUEUE MSMFB_OVERLAY_PLAY 25 26 #define MSMFB_GET_PAGE_PROTECTION _IOR(MSMFB_IOCTL_MAGIC, 138, \ 27 struct mdp_page_protection) 28 #define MSMFB_SET_PAGE_PROTECTION _IOW(MSMFB_IOCTL_MAGIC, 139, \ 29 struct mdp_page_protection) 30 #define MSMFB_OVERLAY_GET _IOR(MSMFB_IOCTL_MAGIC, 140, \ 31 struct mdp_overlay) 32 #define MSMFB_OVERLAY_PLAY_ENABLE _IOW(MSMFB_IOCTL_MAGIC, 141, unsigned int) 33 #define MSMFB_OVERLAY_BLT _IOWR(MSMFB_IOCTL_MAGIC, 142, \ 34 struct msmfb_overlay_blt) 35 #define MSMFB_OVERLAY_BLT_OFFSET _IOW(MSMFB_IOCTL_MAGIC, 143, unsigned int) 36 #define MSMFB_HISTOGRAM_START _IOR(MSMFB_IOCTL_MAGIC, 144, \ 37 struct mdp_histogram_start_req) 38 #define MSMFB_HISTOGRAM_STOP _IOR(MSMFB_IOCTL_MAGIC, 145, unsigned int) 39 #define MSMFB_NOTIFY_UPDATE _IOWR(MSMFB_IOCTL_MAGIC, 146, unsigned int) 40 41 #define MSMFB_OVERLAY_3D _IOWR(MSMFB_IOCTL_MAGIC, 147, \ 42 struct msmfb_overlay_3d) 43 44 #define MSMFB_MIXER_INFO _IOWR(MSMFB_IOCTL_MAGIC, 148, \ 45 struct msmfb_mixer_info_req) 46 #define MSMFB_OVERLAY_PLAY_WAIT _IOWR(MSMFB_IOCTL_MAGIC, 149, \ 47 struct msmfb_overlay_data) 48 #define MSMFB_WRITEBACK_INIT _IO(MSMFB_IOCTL_MAGIC, 150) 49 #define MSMFB_WRITEBACK_START _IO(MSMFB_IOCTL_MAGIC, 151) 50 #define MSMFB_WRITEBACK_STOP _IO(MSMFB_IOCTL_MAGIC, 152) 51 #define MSMFB_WRITEBACK_QUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 153, \ 52 struct msmfb_data) 53 #define MSMFB_WRITEBACK_DEQUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 154, \ 54 struct msmfb_data) 55 #define MSMFB_WRITEBACK_TERMINATE _IO(MSMFB_IOCTL_MAGIC, 155) 56 #define MSMFB_MDP_PP _IOWR(MSMFB_IOCTL_MAGIC, 156, struct msmfb_mdp_pp) 57 #define MSMFB_OVERLAY_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 160, unsigned int) 58 #define MSMFB_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 161, unsigned int) 59 #define MSMFB_BUFFER_SYNC _IOW(MSMFB_IOCTL_MAGIC, 162, struct mdp_buf_sync) 60 #define MSMFB_OVERLAY_COMMIT _IO(MSMFB_IOCTL_MAGIC, 163) 61 #define MSMFB_DISPLAY_COMMIT _IOW(MSMFB_IOCTL_MAGIC, 164, \ 62 struct mdp_display_commit) 63 #define MSMFB_METADATA_SET _IOW(MSMFB_IOCTL_MAGIC, 165, struct msmfb_metadata) 64 #define MSMFB_METADATA_GET _IOW(MSMFB_IOCTL_MAGIC, 166, struct msmfb_metadata) 65 #define MSMFB_WRITEBACK_SET_MIRRORING_HINT _IOW(MSMFB_IOCTL_MAGIC, 167, \ 66 unsigned int) 67 #define MSMFB_ASYNC_BLIT _IOW(MSMFB_IOCTL_MAGIC, 168, unsigned int) 68 #define MSMFB_OVERLAY_PREPARE _IOWR(MSMFB_IOCTL_MAGIC, 169, \ 69 struct mdp_overlay_list) 70 #define MSMFB_LPM_ENABLE _IOWR(MSMFB_IOCTL_MAGIC, 170, unsigned int) 71 72 #define FB_TYPE_3D_PANEL 0x10101010 73 #define MDP_IMGTYPE2_START 0x10000 74 #define MSMFB_DRIVER_VERSION 0xF9E8D701 75 76 /* HW Revisions for different MDSS targets */ 77 #define MDSS_GET_MAJOR(rev) ((rev) >> 28) 78 #define MDSS_GET_MINOR(rev) (((rev) >> 16) & 0xFFF) 79 #define MDSS_GET_STEP(rev) ((rev) & 0xFFFF) 80 #define MDSS_GET_MAJOR_MINOR(rev) ((rev) >> 16) 81 82 #define IS_MDSS_MAJOR_MINOR_SAME(rev1, rev2) \ 83 (MDSS_GET_MAJOR_MINOR((rev1)) == MDSS_GET_MAJOR_MINOR((rev2))) 84 85 #define MDSS_MDP_REV(major, minor, step) \ 86 ((((major) & 0x000F) << 28) | \ 87 (((minor) & 0x0FFF) << 16) | \ 88 ((step) & 0xFFFF)) 89 90 #define MDSS_MDP_HW_REV_100 MDSS_MDP_REV(1, 0, 0) /* 8974 v1.0 */ 91 #define MDSS_MDP_HW_REV_101 MDSS_MDP_REV(1, 1, 0) /* 8x26 v1.0 */ 92 #define MDSS_MDP_HW_REV_101_1 MDSS_MDP_REV(1, 1, 1) /* 8x26 v2.0, 8926 v1.0 */ 93 #define MDSS_MDP_HW_REV_101_2 MDSS_MDP_REV(1, 1, 2) /* 8926 v2.0 */ 94 #define MDSS_MDP_HW_REV_102 MDSS_MDP_REV(1, 2, 0) /* 8974 v2.0 */ 95 #define MDSS_MDP_HW_REV_102_1 MDSS_MDP_REV(1, 2, 1) /* 8974 v3.0 (Pro) */ 96 #define MDSS_MDP_HW_REV_103 MDSS_MDP_REV(1, 3, 0) /* 8084 v1.0 */ 97 #define MDSS_MDP_HW_REV_103_1 MDSS_MDP_REV(1, 3, 1) /* 8084 v1.1 */ 98 #define MDSS_MDP_HW_REV_105 MDSS_MDP_REV(1, 5, 0) /* 8994 v1.0 */ 99 #define MDSS_MDP_HW_REV_106 MDSS_MDP_REV(1, 6, 0) /* 8916 v1.0 */ 100 #define MDSS_MDP_HW_REV_107 MDSS_MDP_REV(1, 7, 0) 101 #define MDSS_MDP_HW_REV_108 MDSS_MDP_REV(1, 8, 0) /* 8939 v1.0 */ 102 #define MDSS_MDP_HW_REV_200 MDSS_MDP_REV(2, 0, 0) /* 8092 v1.0 */ 103 104 enum { 105 NOTIFY_UPDATE_START, 106 NOTIFY_UPDATE_STOP, 107 NOTIFY_UPDATE_POWER_OFF, 108 }; 109 110 enum { 111 NOTIFY_TYPE_NO_UPDATE, 112 NOTIFY_TYPE_SUSPEND, 113 NOTIFY_TYPE_UPDATE, 114 NOTIFY_TYPE_BL_UPDATE, 115 }; 116 117 enum { 118 MDP_RGB_565, /* RGB 565 planer */ 119 MDP_XRGB_8888, /* RGB 888 padded */ 120 MDP_Y_CBCR_H2V2, /* Y and CbCr, pseudo planer w/ Cb is in MSB */ 121 MDP_Y_CBCR_H2V2_ADRENO, 122 MDP_ARGB_8888, /* ARGB 888 */ 123 MDP_RGB_888, /* RGB 888 planer */ 124 MDP_Y_CRCB_H2V2, /* Y and CrCb, pseudo planer w/ Cr is in MSB */ 125 MDP_YCRYCB_H2V1, /* YCrYCb interleave */ 126 MDP_CBYCRY_H2V1, /* CbYCrY interleave */ 127 MDP_Y_CRCB_H2V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */ 128 MDP_Y_CBCR_H2V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */ 129 MDP_Y_CRCB_H1V2, 130 MDP_Y_CBCR_H1V2, 131 MDP_RGBA_8888, /* ARGB 888 */ 132 MDP_BGRA_8888, /* ABGR 888 */ 133 MDP_RGBX_8888, /* RGBX 888 */ 134 MDP_Y_CRCB_H2V2_TILE, /* Y and CrCb, pseudo planer tile */ 135 MDP_Y_CBCR_H2V2_TILE, /* Y and CbCr, pseudo planer tile */ 136 MDP_Y_CR_CB_H2V2, /* Y, Cr and Cb, planar */ 137 MDP_Y_CR_CB_GH2V2, /* Y, Cr and Cb, planar aligned to Android YV12 */ 138 MDP_Y_CB_CR_H2V2, /* Y, Cb and Cr, planar */ 139 MDP_Y_CRCB_H1V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */ 140 MDP_Y_CBCR_H1V1, /* Y and CbCr, pseduo planer w/ Cb is in MSB */ 141 MDP_YCRCB_H1V1, /* YCrCb interleave */ 142 MDP_YCBCR_H1V1, /* YCbCr interleave */ 143 MDP_BGR_565, /* BGR 565 planer */ 144 MDP_BGR_888, /* BGR 888 */ 145 MDP_Y_CBCR_H2V2_VENUS, 146 MDP_BGRX_8888, /* BGRX 8888 */ 147 MDP_RGBA_8888_TILE, /* RGBA 8888 in tile format */ 148 MDP_ARGB_8888_TILE, /* ARGB 8888 in tile format */ 149 MDP_ABGR_8888_TILE, /* ABGR 8888 in tile format */ 150 MDP_BGRA_8888_TILE, /* BGRA 8888 in tile format */ 151 MDP_RGBX_8888_TILE, /* RGBX 8888 in tile format */ 152 MDP_XRGB_8888_TILE, /* XRGB 8888 in tile format */ 153 MDP_XBGR_8888_TILE, /* XBGR 8888 in tile format */ 154 MDP_BGRX_8888_TILE, /* BGRX 8888 in tile format */ 155 MDP_YCBYCR_H2V1, /* YCbYCr interleave */ 156 MDP_RGB_565_TILE, /* RGB 565 in tile format */ 157 MDP_BGR_565_TILE, /* BGR 565 in tile format */ 158 MDP_IMGTYPE_LIMIT, 159 MDP_RGB_BORDERFILL, /* border fill pipe */ 160 MDP_FB_FORMAT = MDP_IMGTYPE2_START, /* framebuffer format */ 161 MDP_IMGTYPE_LIMIT2 /* Non valid image type after this enum */ 162 }; 163 164 enum { 165 PMEM_IMG, 166 FB_IMG, 167 }; 168 169 enum { 170 HSIC_HUE = 0, 171 HSIC_SAT, 172 HSIC_INT, 173 HSIC_CON, 174 NUM_HSIC_PARAM, 175 }; 176 177 #define MDSS_MDP_ROT_ONLY 0x80 178 #define MDSS_MDP_RIGHT_MIXER 0x100 179 #define MDSS_MDP_DUAL_PIPE 0x200 180 181 /* mdp_blit_req flag values */ 182 #define MDP_ROT_NOP 0 183 #define MDP_FLIP_LR 0x1 184 #define MDP_FLIP_UD 0x2 185 #define MDP_ROT_90 0x4 186 #define MDP_ROT_180 (MDP_FLIP_UD|MDP_FLIP_LR) 187 #define MDP_ROT_270 (MDP_ROT_90|MDP_FLIP_UD|MDP_FLIP_LR) 188 #define MDP_DITHER 0x8 189 #define MDP_BLUR 0x10 190 #define MDP_BLEND_FG_PREMULT 0x20000 191 #define MDP_IS_FG 0x40000 192 #define MDP_SOLID_FILL 0x00000020 193 #define MDP_VPU_PIPE 0x00000040 194 #define MDP_DEINTERLACE 0x80000000 195 #define MDP_SHARPENING 0x40000000 196 #define MDP_NO_DMA_BARRIER_START 0x20000000 197 #define MDP_NO_DMA_BARRIER_END 0x10000000 198 #define MDP_NO_BLIT 0x08000000 199 #define MDP_BLIT_WITH_DMA_BARRIERS 0x000 200 #define MDP_BLIT_WITH_NO_DMA_BARRIERS \ 201 (MDP_NO_DMA_BARRIER_START | MDP_NO_DMA_BARRIER_END) 202 #define MDP_BLIT_SRC_GEM 0x04000000 203 #define MDP_BLIT_DST_GEM 0x02000000 204 #define MDP_BLIT_NON_CACHED 0x01000000 205 #define MDP_OV_PIPE_SHARE 0x00800000 206 #define MDP_DEINTERLACE_ODD 0x00400000 207 #define MDP_OV_PLAY_NOWAIT 0x00200000 208 #define MDP_SOURCE_ROTATED_90 0x00100000 209 #define MDP_OVERLAY_PP_CFG_EN 0x00080000 210 #define MDP_BACKEND_COMPOSITION 0x00040000 211 #define MDP_BORDERFILL_SUPPORTED 0x00010000 212 #define MDP_SECURE_OVERLAY_SESSION 0x00008000 213 #define MDP_SECURE_DISPLAY_OVERLAY_SESSION 0x00002000 214 #define MDP_OV_PIPE_FORCE_DMA 0x00004000 215 #define MDP_MEMORY_ID_TYPE_FB 0x00001000 216 #define MDP_BWC_EN 0x00000400 217 #define MDP_DECIMATION_EN 0x00000800 218 #define MDP_TRANSP_NOP 0xffffffff 219 #define MDP_ALPHA_NOP 0xff 220 221 #define MDP_FB_PAGE_PROTECTION_NONCACHED (0) 222 #define MDP_FB_PAGE_PROTECTION_WRITECOMBINE (1) 223 #define MDP_FB_PAGE_PROTECTION_WRITETHROUGHCACHE (2) 224 #define MDP_FB_PAGE_PROTECTION_WRITEBACKCACHE (3) 225 #define MDP_FB_PAGE_PROTECTION_WRITEBACKWACACHE (4) 226 /* Sentinel: Don't use! */ 227 #define MDP_FB_PAGE_PROTECTION_INVALID (5) 228 /* Count of the number of MDP_FB_PAGE_PROTECTION_... values. */ 229 #define MDP_NUM_FB_PAGE_PROTECTION_VALUES (5) 230 231 struct mdp_rect { 232 uint32_t x; 233 uint32_t y; 234 uint32_t w; 235 uint32_t h; 236 }; 237 238 struct mdp_img { 239 uint32_t width; 240 uint32_t height; 241 uint32_t format; 242 uint32_t offset; 243 int memory_id; /* the file descriptor */ 244 uint32_t priv; 245 }; 246 247 /* 248 * {3x3} + {3} ccs matrix 249 */ 250 251 #define MDP_CCS_RGB2YUV 0 252 #define MDP_CCS_YUV2RGB 1 253 254 #define MDP_CCS_SIZE 9 255 #define MDP_BV_SIZE 3 256 257 struct mdp_ccs { 258 int direction; /* MDP_CCS_RGB2YUV or YUV2RGB */ 259 uint16_t ccs[MDP_CCS_SIZE]; /* 3x3 color coefficients */ 260 uint16_t bv[MDP_BV_SIZE]; /* 1x3 bias vector */ 261 }; 262 263 struct mdp_csc { 264 int id; 265 uint32_t csc_mv[9]; 266 uint32_t csc_pre_bv[3]; 267 uint32_t csc_post_bv[3]; 268 uint32_t csc_pre_lv[6]; 269 uint32_t csc_post_lv[6]; 270 }; 271 272 /* The version of the mdp_blit_req structure so that 273 * user applications can selectively decide which functionality 274 * to include 275 */ 276 277 #define MDP_BLIT_REQ_VERSION 2 278 279 struct color { 280 uint32_t r; 281 uint32_t g; 282 uint32_t b; 283 uint32_t alpha; 284 }; 285 286 struct mdp_blit_req { 287 struct mdp_img src; 288 struct mdp_img dst; 289 struct mdp_rect src_rect; 290 struct mdp_rect dst_rect; 291 struct color const_color; 292 uint32_t alpha; 293 uint32_t transp_mask; 294 uint32_t flags; 295 int sharpening_strength; /* -127 <--> 127, default 64 */ 296 }; 297 298 struct mdp_blit_req_list { 299 uint32_t count; 300 struct mdp_blit_req req[]; 301 }; 302 303 #define MSMFB_DATA_VERSION 2 304 305 struct msmfb_data { 306 uint32_t offset; 307 int memory_id; 308 int id; 309 uint32_t flags; 310 uint32_t priv; 311 uint32_t iova; 312 }; 313 314 #define MSMFB_NEW_REQUEST -1 315 316 struct msmfb_overlay_data { 317 uint32_t id; 318 struct msmfb_data data; 319 uint32_t version_key; 320 struct msmfb_data plane1_data; 321 struct msmfb_data plane2_data; 322 struct msmfb_data dst_data; 323 }; 324 325 struct msmfb_img { 326 uint32_t width; 327 uint32_t height; 328 uint32_t format; 329 }; 330 331 #define MSMFB_WRITEBACK_DEQUEUE_BLOCKING 0x1 332 struct msmfb_writeback_data { 333 struct msmfb_data buf_info; 334 struct msmfb_img img; 335 }; 336 337 #define MDP_PP_OPS_ENABLE 0x1 338 #define MDP_PP_OPS_READ 0x2 339 #define MDP_PP_OPS_WRITE 0x4 340 #define MDP_PP_OPS_DISABLE 0x8 341 #define MDP_PP_IGC_FLAG_ROM0 0x10 342 #define MDP_PP_IGC_FLAG_ROM1 0x20 343 344 #define MDP_PP_PA_HUE_ENABLE 0x10 345 #define MDP_PP_PA_SAT_ENABLE 0x20 346 #define MDP_PP_PA_VAL_ENABLE 0x40 347 #define MDP_PP_PA_CONT_ENABLE 0x80 348 #define MDP_PP_PA_SIX_ZONE_ENABLE 0x100 349 #define MDP_PP_PA_SKIN_ENABLE 0x200 350 #define MDP_PP_PA_SKY_ENABLE 0x400 351 #define MDP_PP_PA_FOL_ENABLE 0x800 352 #define MDP_PP_PA_HUE_MASK 0x1000 353 #define MDP_PP_PA_SAT_MASK 0x2000 354 #define MDP_PP_PA_VAL_MASK 0x4000 355 #define MDP_PP_PA_CONT_MASK 0x8000 356 #define MDP_PP_PA_SIX_ZONE_HUE_MASK 0x10000 357 #define MDP_PP_PA_SIX_ZONE_SAT_MASK 0x20000 358 #define MDP_PP_PA_SIX_ZONE_VAL_MASK 0x40000 359 #define MDP_PP_PA_MEM_COL_SKIN_MASK 0x80000 360 #define MDP_PP_PA_MEM_COL_SKY_MASK 0x100000 361 #define MDP_PP_PA_MEM_COL_FOL_MASK 0x200000 362 #define MDP_PP_PA_MEM_PROTECT_EN 0x400000 363 #define MDP_PP_PA_SAT_ZERO_EXP_EN 0x800000 364 365 #define MDSS_PP_DSPP_CFG 0x000 366 #define MDSS_PP_SSPP_CFG 0x100 367 #define MDSS_PP_LM_CFG 0x200 368 #define MDSS_PP_WB_CFG 0x300 369 370 #define MDSS_PP_ARG_MASK 0x3C00 371 #define MDSS_PP_ARG_NUM 4 372 #define MDSS_PP_ARG_SHIFT 10 373 #define MDSS_PP_LOCATION_MASK 0x0300 374 #define MDSS_PP_LOGICAL_MASK 0x00FF 375 376 #define MDSS_PP_ADD_ARG(var, arg) ((var) | (0x1 << (MDSS_PP_ARG_SHIFT + (arg)))) 377 #define PP_ARG(x, var) ((var) & (0x1 << (MDSS_PP_ARG_SHIFT + (x)))) 378 #define PP_LOCAT(var) ((var) & MDSS_PP_LOCATION_MASK) 379 #define PP_BLOCK(var) ((var) & MDSS_PP_LOGICAL_MASK) 380 381 382 struct mdp_qseed_cfg { 383 uint32_t table_num; 384 uint32_t ops; 385 uint32_t len; 386 uint32_t *data; 387 }; 388 389 struct mdp_sharp_cfg { 390 uint32_t flags; 391 uint32_t strength; 392 uint32_t edge_thr; 393 uint32_t smooth_thr; 394 uint32_t noise_thr; 395 }; 396 397 struct mdp_qseed_cfg_data { 398 uint32_t block; 399 struct mdp_qseed_cfg qseed_data; 400 }; 401 402 #define MDP_OVERLAY_PP_CSC_CFG 0x1 403 #define MDP_OVERLAY_PP_QSEED_CFG 0x2 404 #define MDP_OVERLAY_PP_PA_CFG 0x4 405 #define MDP_OVERLAY_PP_IGC_CFG 0x8 406 #define MDP_OVERLAY_PP_SHARP_CFG 0x10 407 #define MDP_OVERLAY_PP_HIST_CFG 0x20 408 #define MDP_OVERLAY_PP_HIST_LUT_CFG 0x40 409 #define MDP_OVERLAY_PP_PA_V2_CFG 0x80 410 411 #define MDP_CSC_FLAG_ENABLE 0x1 412 #define MDP_CSC_FLAG_YUV_IN 0x2 413 #define MDP_CSC_FLAG_YUV_OUT 0x4 414 415 struct mdp_csc_cfg { 416 /* flags for enable CSC, toggling RGB,YUV input/output */ 417 uint32_t flags; 418 uint32_t csc_mv[9]; 419 uint32_t csc_pre_bv[3]; 420 uint32_t csc_post_bv[3]; 421 uint32_t csc_pre_lv[6]; 422 uint32_t csc_post_lv[6]; 423 }; 424 425 struct mdp_csc_cfg_data { 426 uint32_t block; 427 struct mdp_csc_cfg csc_data; 428 }; 429 430 struct mdp_pa_cfg { 431 uint32_t flags; 432 uint32_t hue_adj; 433 uint32_t sat_adj; 434 uint32_t val_adj; 435 uint32_t cont_adj; 436 }; 437 438 struct mdp_pa_mem_col_cfg { 439 uint32_t color_adjust_p0; 440 uint32_t color_adjust_p1; 441 uint32_t hue_region; 442 uint32_t sat_region; 443 uint32_t val_region; 444 }; 445 446 #define MDP_SIX_ZONE_LUT_SIZE 384 447 448 struct mdp_pa_v2_data { 449 /* Mask bits for PA features */ 450 uint32_t flags; 451 uint32_t global_hue_adj; 452 uint32_t global_sat_adj; 453 uint32_t global_val_adj; 454 uint32_t global_cont_adj; 455 struct mdp_pa_mem_col_cfg skin_cfg; 456 struct mdp_pa_mem_col_cfg sky_cfg; 457 struct mdp_pa_mem_col_cfg fol_cfg; 458 uint32_t six_zone_len; 459 uint32_t six_zone_thresh; 460 uint32_t *six_zone_curve_p0; 461 uint32_t *six_zone_curve_p1; 462 }; 463 464 struct mdp_igc_lut_data { 465 uint32_t block; 466 uint32_t len, ops; 467 uint32_t *c0_c1_data; 468 uint32_t *c2_data; 469 }; 470 471 struct mdp_histogram_cfg { 472 uint32_t ops; 473 uint32_t block; 474 uint8_t frame_cnt; 475 uint8_t bit_mask; 476 uint16_t num_bins; 477 }; 478 479 struct mdp_hist_lut_data { 480 uint32_t block; 481 uint32_t ops; 482 uint32_t len; 483 uint32_t *data; 484 }; 485 486 struct mdp_overlay_pp_params { 487 uint32_t config_ops; 488 struct mdp_csc_cfg csc_cfg; 489 struct mdp_qseed_cfg qseed_cfg[2]; 490 struct mdp_pa_cfg pa_cfg; 491 struct mdp_pa_v2_data pa_v2_cfg; 492 struct mdp_igc_lut_data igc_cfg; 493 struct mdp_sharp_cfg sharp_cfg; 494 struct mdp_histogram_cfg hist_cfg; 495 struct mdp_hist_lut_data hist_lut_cfg; 496 }; 497 498 /** 499 * enum mdss_mdp_blend_op - Different blend operations set by userspace 500 * 501 * @BLEND_OP_NOT_DEFINED: No blend operation defined for the layer. 502 * @BLEND_OP_OPAQUE: Apply a constant blend operation. The layer 503 * would appear opaque in case fg plane alpha is 504 * 0xff. 505 * @BLEND_OP_PREMULTIPLIED: Apply source over blend rule. Layer already has 506 * alpha pre-multiplication done. If fg plane alpha 507 * is less than 0xff, apply modulation as well. This 508 * operation is intended on layers having alpha 509 * channel. 510 * @BLEND_OP_COVERAGE: Apply source over blend rule. Layer is not alpha 511 * pre-multiplied. Apply pre-multiplication. If fg 512 * plane alpha is less than 0xff, apply modulation as 513 * well. 514 * @BLEND_OP_MAX: Used to track maximum blend operation possible by 515 * mdp. 516 */ 517 enum mdss_mdp_blend_op { 518 BLEND_OP_NOT_DEFINED = 0, 519 BLEND_OP_OPAQUE, 520 BLEND_OP_PREMULTIPLIED, 521 BLEND_OP_COVERAGE, 522 BLEND_OP_MAX, 523 }; 524 525 #define MAX_PLANES 4 526 struct mdp_scale_data { 527 uint8_t enable_pxl_ext; 528 529 int init_phase_x[MAX_PLANES]; 530 int phase_step_x[MAX_PLANES]; 531 int init_phase_y[MAX_PLANES]; 532 int phase_step_y[MAX_PLANES]; 533 534 int num_ext_pxls_left[MAX_PLANES]; 535 int num_ext_pxls_right[MAX_PLANES]; 536 int num_ext_pxls_top[MAX_PLANES]; 537 int num_ext_pxls_btm[MAX_PLANES]; 538 539 int left_ftch[MAX_PLANES]; 540 int left_rpt[MAX_PLANES]; 541 int right_ftch[MAX_PLANES]; 542 int right_rpt[MAX_PLANES]; 543 544 int top_rpt[MAX_PLANES]; 545 int btm_rpt[MAX_PLANES]; 546 int top_ftch[MAX_PLANES]; 547 int btm_ftch[MAX_PLANES]; 548 549 uint32_t roi_w[MAX_PLANES]; 550 }; 551 552 /** 553 * enum mdp_overlay_pipe_type - Different pipe type set by userspace 554 * 555 * @PIPE_TYPE_AUTO: Not specified, pipe will be selected according to flags. 556 * @PIPE_TYPE_VIG: VIG pipe. 557 * @PIPE_TYPE_RGB: RGB pipe. 558 * @PIPE_TYPE_DMA: DMA pipe. 559 * @PIPE_TYPE_CURSOR: CURSOR pipe. 560 * @PIPE_TYPE_MAX: Used to track maximum number of pipe type. 561 */ 562 enum mdp_overlay_pipe_type { 563 PIPE_TYPE_AUTO = 0, 564 PIPE_TYPE_VIG, 565 PIPE_TYPE_RGB, 566 PIPE_TYPE_DMA, 567 PIPE_TYPE_CURSOR, 568 PIPE_TYPE_MAX, 569 }; 570 571 /** 572 * struct mdp_overlay - overlay surface structure 573 * @src: Source image information (width, height, format). 574 * @src_rect: Source crop rectangle, portion of image that will be fetched. 575 * This should always be within boundaries of source image. 576 * @dst_rect: Destination rectangle, the position and size of image on screen. 577 * This should always be within panel boundaries. 578 * @z_order: Blending stage to occupy in display, if multiple layers are 579 * present, highest z_order usually means the top most visible 580 * layer. The range acceptable is from 0-3 to support blending 581 * up to 4 layers. 582 * @is_fg: This flag is used to disable blending of any layers with z_order 583 * less than this overlay. It means that any layers with z_order 584 * less than this layer will not be blended and will be replaced 585 * by the background border color. 586 * @alpha: Used to set plane opacity. The range can be from 0-255, where 587 * 0 means completely transparent and 255 means fully opaque. 588 * @transp_mask: Color used as color key for transparency. Any pixel in fetched 589 * image matching this color will be transparent when blending. 590 * The color should be in same format as the source image format. 591 * @flags: This is used to customize operation of overlay. See MDP flags 592 * for more information. 593 * @pipe_type: Used to specify the type of overlay pipe. 594 * @user_data: DEPRECATED* Used to store user application specific information. 595 * @bg_color: Solid color used to fill the overlay surface when no source 596 * buffer is provided. 597 * @horz_deci: Horizontal decimation value, this indicates the amount of pixels 598 * dropped for each pixel that is fetched from a line. The value 599 * given should be power of two of decimation amount. 600 * 0: no decimation 601 * 1: decimate by 2 (drop 1 pixel for each pixel fetched) 602 * 2: decimate by 4 (drop 3 pixels for each pixel fetched) 603 * 3: decimate by 8 (drop 7 pixels for each pixel fetched) 604 * 4: decimate by 16 (drop 15 pixels for each pixel fetched) 605 * @vert_deci: Vertical decimation value, this indicates the amount of lines 606 * dropped for each line that is fetched from overlay. The value 607 * given should be power of two of decimation amount. 608 * 0: no decimation 609 * 1: decimation by 2 (drop 1 line for each line fetched) 610 * 2: decimation by 4 (drop 3 lines for each line fetched) 611 * 3: decimation by 8 (drop 7 lines for each line fetched) 612 * 4: decimation by 16 (drop 15 lines for each line fetched) 613 * @overlay_pp_cfg: Overlay post processing configuration, for more information 614 * see struct mdp_overlay_pp_params. 615 * @priority: Priority is returned by the driver when overlay is set for the 616 * first time. It indicates the priority of the underlying pipe 617 * serving the overlay. This priority can be used by user-space 618 * in source split when pipes are re-used and shuffled around to 619 * reduce fallbacks. 620 */ 621 struct mdp_overlay { 622 struct msmfb_img src; 623 struct mdp_rect src_rect; 624 struct mdp_rect dst_rect; 625 uint32_t z_order; /* stage number */ 626 uint32_t is_fg; /* control alpha & transp */ 627 uint32_t alpha; 628 uint32_t blend_op; 629 uint32_t transp_mask; 630 uint32_t flags; 631 uint32_t pipe_type; 632 uint32_t id; 633 uint8_t priority; 634 uint32_t user_data[6]; 635 uint32_t bg_color; 636 uint8_t horz_deci; 637 uint8_t vert_deci; 638 struct mdp_overlay_pp_params overlay_pp_cfg; 639 struct mdp_scale_data scale; 640 }; 641 642 struct msmfb_overlay_3d { 643 uint32_t is_3d; 644 uint32_t width; 645 uint32_t height; 646 }; 647 648 649 struct msmfb_overlay_blt { 650 uint32_t enable; 651 uint32_t offset; 652 uint32_t width; 653 uint32_t height; 654 uint32_t bpp; 655 }; 656 657 struct mdp_histogram { 658 uint32_t frame_cnt; 659 uint32_t bin_cnt; 660 uint32_t *r; 661 uint32_t *g; 662 uint32_t *b; 663 }; 664 665 #define MISR_CRC_BATCH_SIZE 32 666 enum { 667 DISPLAY_MISR_EDP, 668 DISPLAY_MISR_DSI0, 669 DISPLAY_MISR_DSI1, 670 DISPLAY_MISR_HDMI, 671 DISPLAY_MISR_LCDC, 672 DISPLAY_MISR_MDP, 673 DISPLAY_MISR_ATV, 674 DISPLAY_MISR_DSI_CMD, 675 DISPLAY_MISR_MAX 676 }; 677 678 enum { 679 MISR_OP_NONE, 680 MISR_OP_SFM, 681 MISR_OP_MFM, 682 MISR_OP_BM, 683 MISR_OP_MAX 684 }; 685 686 struct mdp_misr { 687 uint32_t block_id; 688 uint32_t frame_count; 689 uint32_t crc_op_mode; 690 uint32_t crc_value[MISR_CRC_BATCH_SIZE]; 691 }; 692 693 /* 694 695 mdp_block_type defines the identifiers for pipes in MDP 4.3 and up 696 697 MDP_BLOCK_RESERVED is provided for backward compatibility and is 698 deprecated. It corresponds to DMA_P. So MDP_BLOCK_DMA_P should be used 699 instead. 700 701 MDP_LOGICAL_BLOCK_DISP_0 identifies the display pipe which fb0 uses, 702 same for others. 703 704 */ 705 706 enum { 707 MDP_BLOCK_RESERVED = 0, 708 MDP_BLOCK_OVERLAY_0, 709 MDP_BLOCK_OVERLAY_1, 710 MDP_BLOCK_VG_1, 711 MDP_BLOCK_VG_2, 712 MDP_BLOCK_RGB_1, 713 MDP_BLOCK_RGB_2, 714 MDP_BLOCK_DMA_P, 715 MDP_BLOCK_DMA_S, 716 MDP_BLOCK_DMA_E, 717 MDP_BLOCK_OVERLAY_2, 718 MDP_LOGICAL_BLOCK_DISP_0 = 0x10, 719 MDP_LOGICAL_BLOCK_DISP_1, 720 MDP_LOGICAL_BLOCK_DISP_2, 721 MDP_BLOCK_MAX, 722 }; 723 724 /* 725 * mdp_histogram_start_req is used to provide the parameters for 726 * histogram start request 727 */ 728 729 struct mdp_histogram_start_req { 730 uint32_t block; 731 uint8_t frame_cnt; 732 uint8_t bit_mask; 733 uint16_t num_bins; 734 }; 735 736 /* 737 * mdp_histogram_data is used to return the histogram data, once 738 * the histogram is done/stopped/cance 739 */ 740 741 struct mdp_histogram_data { 742 uint32_t block; 743 uint32_t bin_cnt; 744 uint32_t *c0; 745 uint32_t *c1; 746 uint32_t *c2; 747 uint32_t *extra_info; 748 }; 749 750 struct mdp_pcc_coeff { 751 uint32_t c, r, g, b, rr, gg, bb, rg, gb, rb, rgb_0, rgb_1; 752 }; 753 754 struct mdp_pcc_cfg_data { 755 uint32_t block; 756 uint32_t ops; 757 struct mdp_pcc_coeff r, g, b; 758 }; 759 760 #define MDP_GAMUT_TABLE_NUM 8 761 762 enum { 763 mdp_lut_igc, 764 mdp_lut_pgc, 765 mdp_lut_hist, 766 mdp_lut_max, 767 }; 768 769 struct mdp_ar_gc_lut_data { 770 uint32_t x_start; 771 uint32_t slope; 772 uint32_t offset; 773 }; 774 775 struct mdp_pgc_lut_data { 776 uint32_t block; 777 uint32_t flags; 778 uint8_t num_r_stages; 779 uint8_t num_g_stages; 780 uint8_t num_b_stages; 781 struct mdp_ar_gc_lut_data *r_data; 782 struct mdp_ar_gc_lut_data *g_data; 783 struct mdp_ar_gc_lut_data *b_data; 784 }; 785 786 787 struct mdp_lut_cfg_data { 788 uint32_t lut_type; 789 union { 790 struct mdp_igc_lut_data igc_lut_data; 791 struct mdp_pgc_lut_data pgc_lut_data; 792 struct mdp_hist_lut_data hist_lut_data; 793 } data; 794 }; 795 796 struct mdp_bl_scale_data { 797 uint32_t min_lvl; 798 uint32_t scale; 799 }; 800 801 struct mdp_pa_cfg_data { 802 uint32_t block; 803 struct mdp_pa_cfg pa_data; 804 }; 805 806 struct mdp_pa_v2_cfg_data { 807 uint32_t block; 808 struct mdp_pa_v2_data pa_v2_data; 809 }; 810 811 struct mdp_dither_cfg_data { 812 uint32_t block; 813 uint32_t flags; 814 uint32_t g_y_depth; 815 uint32_t r_cr_depth; 816 uint32_t b_cb_depth; 817 }; 818 819 struct mdp_gamut_cfg_data { 820 uint32_t block; 821 uint32_t flags; 822 uint32_t gamut_first; 823 uint32_t tbl_size[MDP_GAMUT_TABLE_NUM]; 824 uint16_t *r_tbl[MDP_GAMUT_TABLE_NUM]; 825 uint16_t *g_tbl[MDP_GAMUT_TABLE_NUM]; 826 uint16_t *b_tbl[MDP_GAMUT_TABLE_NUM]; 827 }; 828 829 struct mdp_calib_config_data { 830 uint32_t ops; 831 uint32_t addr; 832 uint32_t data; 833 }; 834 835 struct mdp_calib_config_buffer { 836 uint32_t ops; 837 uint32_t size; 838 uint32_t *buffer; 839 }; 840 841 struct mdp_calib_dcm_state { 842 uint32_t ops; 843 uint32_t dcm_state; 844 }; 845 846 enum { 847 DCM_UNINIT, 848 DCM_UNBLANK, 849 DCM_ENTER, 850 DCM_EXIT, 851 DCM_BLANK, 852 DTM_ENTER, 853 DTM_EXIT, 854 }; 855 856 #define MDSS_PP_SPLIT_LEFT_ONLY 0x10000000 857 #define MDSS_PP_SPLIT_RIGHT_ONLY 0x20000000 858 #define MDSS_PP_SPLIT_MASK 0x30000000 859 860 #define MDSS_MAX_BL_BRIGHTNESS 255 861 #define AD_BL_LIN_LEN 256 862 #define AD_BL_ATT_LUT_LEN 33 863 864 #define MDSS_AD_MODE_AUTO_BL 0x0 865 #define MDSS_AD_MODE_AUTO_STR 0x1 866 #define MDSS_AD_MODE_TARG_STR 0x3 867 #define MDSS_AD_MODE_MAN_STR 0x7 868 #define MDSS_AD_MODE_CALIB 0xF 869 870 #define MDP_PP_AD_INIT 0x10 871 #define MDP_PP_AD_CFG 0x20 872 873 struct mdss_ad_init { 874 uint32_t asym_lut[33]; 875 uint32_t color_corr_lut[33]; 876 uint8_t i_control[2]; 877 uint16_t black_lvl; 878 uint16_t white_lvl; 879 uint8_t var; 880 uint8_t limit_ampl; 881 uint8_t i_dither; 882 uint8_t slope_max; 883 uint8_t slope_min; 884 uint8_t dither_ctl; 885 uint8_t format; 886 uint8_t auto_size; 887 uint16_t frame_w; 888 uint16_t frame_h; 889 uint8_t logo_v; 890 uint8_t logo_h; 891 uint32_t alpha; 892 uint32_t alpha_base; 893 uint32_t bl_lin_len; 894 uint32_t bl_att_len; 895 uint32_t *bl_lin; 896 uint32_t *bl_lin_inv; 897 uint32_t *bl_att_lut; 898 }; 899 900 #define MDSS_AD_BL_CTRL_MODE_EN 1 901 #define MDSS_AD_BL_CTRL_MODE_DIS 0 902 struct mdss_ad_cfg { 903 uint32_t mode; 904 uint32_t al_calib_lut[33]; 905 uint16_t backlight_min; 906 uint16_t backlight_max; 907 uint16_t backlight_scale; 908 uint16_t amb_light_min; 909 uint16_t filter[2]; 910 uint16_t calib[4]; 911 uint8_t strength_limit; 912 uint8_t t_filter_recursion; 913 uint16_t stab_itr; 914 uint32_t bl_ctrl_mode; 915 }; 916 917 /* ops uses standard MDP_PP_* flags */ 918 struct mdss_ad_init_cfg { 919 uint32_t ops; 920 union { 921 struct mdss_ad_init init; 922 struct mdss_ad_cfg cfg; 923 } params; 924 }; 925 926 /* mode uses MDSS_AD_MODE_* flags */ 927 struct mdss_ad_input { 928 uint32_t mode; 929 union { 930 uint32_t amb_light; 931 uint32_t strength; 932 uint32_t calib_bl; 933 } in; 934 uint32_t output; 935 }; 936 937 #define MDSS_CALIB_MODE_BL 0x1 938 struct mdss_calib_cfg { 939 uint32_t ops; 940 uint32_t calib_mask; 941 }; 942 943 enum { 944 mdp_op_pcc_cfg, 945 mdp_op_csc_cfg, 946 mdp_op_lut_cfg, 947 mdp_op_qseed_cfg, 948 mdp_bl_scale_cfg, 949 mdp_op_pa_cfg, 950 mdp_op_pa_v2_cfg, 951 mdp_op_dither_cfg, 952 mdp_op_gamut_cfg, 953 mdp_op_calib_cfg, 954 mdp_op_ad_cfg, 955 mdp_op_ad_input, 956 mdp_op_calib_mode, 957 mdp_op_calib_buffer, 958 mdp_op_calib_dcm_state, 959 mdp_op_max, 960 }; 961 962 enum { 963 WB_FORMAT_NV12, 964 WB_FORMAT_RGB_565, 965 WB_FORMAT_RGB_888, 966 WB_FORMAT_xRGB_8888, 967 WB_FORMAT_ARGB_8888, 968 WB_FORMAT_BGRA_8888, 969 WB_FORMAT_BGRX_8888, 970 WB_FORMAT_ARGB_8888_INPUT_ALPHA /* Need to support */ 971 }; 972 973 struct msmfb_mdp_pp { 974 uint32_t op; 975 union { 976 struct mdp_pcc_cfg_data pcc_cfg_data; 977 struct mdp_csc_cfg_data csc_cfg_data; 978 struct mdp_lut_cfg_data lut_cfg_data; 979 struct mdp_qseed_cfg_data qseed_cfg_data; 980 struct mdp_bl_scale_data bl_scale_data; 981 struct mdp_pa_cfg_data pa_cfg_data; 982 struct mdp_pa_v2_cfg_data pa_v2_cfg_data; 983 struct mdp_dither_cfg_data dither_cfg_data; 984 struct mdp_gamut_cfg_data gamut_cfg_data; 985 struct mdp_calib_config_data calib_cfg; 986 struct mdss_ad_init_cfg ad_init_cfg; 987 struct mdss_calib_cfg mdss_calib_cfg; 988 struct mdss_ad_input ad_input; 989 struct mdp_calib_config_buffer calib_buffer; 990 struct mdp_calib_dcm_state calib_dcm; 991 } data; 992 }; 993 994 #define FB_METADATA_VIDEO_INFO_CODE_SUPPORT 1 995 enum { 996 metadata_op_none, 997 metadata_op_base_blend, 998 metadata_op_frame_rate, 999 metadata_op_vic, 1000 metadata_op_wb_format, 1001 metadata_op_wb_secure, 1002 metadata_op_get_caps, 1003 metadata_op_crc, 1004 metadata_op_get_ion_fd, 1005 metadata_op_max 1006 }; 1007 1008 struct mdp_blend_cfg { 1009 uint32_t is_premultiplied; 1010 }; 1011 1012 struct mdp_mixer_cfg { 1013 uint32_t writeback_format; 1014 uint32_t alpha; 1015 }; 1016 1017 struct mdss_hw_caps { 1018 uint32_t mdp_rev; 1019 uint8_t rgb_pipes; 1020 uint8_t vig_pipes; 1021 uint8_t dma_pipes; 1022 uint8_t max_smp_cnt; 1023 uint8_t smp_per_pipe; 1024 uint32_t features; 1025 }; 1026 1027 struct msmfb_metadata { 1028 uint32_t op; 1029 uint32_t flags; 1030 union { 1031 struct mdp_misr misr_request; 1032 struct mdp_blend_cfg blend_cfg; 1033 struct mdp_mixer_cfg mixer_cfg; 1034 uint32_t panel_frame_rate; 1035 uint32_t video_info_code; 1036 struct mdss_hw_caps caps; 1037 uint8_t secure_en; 1038 int fbmem_ionfd; 1039 } data; 1040 }; 1041 1042 #define MDP_MAX_FENCE_FD 32 1043 #define MDP_BUF_SYNC_FLAG_WAIT 1 1044 #define MDP_BUF_SYNC_FLAG_RETIRE_FENCE 0x10 1045 1046 struct mdp_buf_sync { 1047 uint32_t flags; 1048 uint32_t acq_fen_fd_cnt; 1049 uint32_t session_id; 1050 int *acq_fen_fd; 1051 int *rel_fen_fd; 1052 int *retire_fen_fd; 1053 }; 1054 1055 struct mdp_async_blit_req_list { 1056 struct mdp_buf_sync sync; 1057 uint32_t count; 1058 struct mdp_blit_req req[]; 1059 }; 1060 1061 #define MDP_DISPLAY_COMMIT_OVERLAY 1 1062 1063 struct mdp_display_commit { 1064 uint32_t flags; 1065 uint32_t wait_for_finish; 1066 struct fb_var_screeninfo var; 1067 struct mdp_rect l_roi; 1068 struct mdp_rect r_roi; 1069 }; 1070 1071 /** 1072 * struct mdp_overlay_list - argument for ioctl MSMFB_OVERLAY_PREPARE 1073 * @num_overlays: Number of overlay layers as part of the frame. 1074 * @overlay_list: Pointer to a list of overlay structures identifying 1075 * the layers as part of the frame 1076 * @flags: Flags can be used to extend behavior. 1077 * @processed_overlays: Output parameter indicating how many pipes were 1078 * successful. If there are no errors this number should 1079 * match num_overlays. Otherwise it will indicate the last 1080 * successful index for overlay that couldn't be set. 1081 */ 1082 struct mdp_overlay_list { 1083 uint32_t num_overlays; 1084 struct mdp_overlay **overlay_list; 1085 uint32_t flags; 1086 uint32_t processed_overlays; 1087 }; 1088 1089 struct mdp_page_protection { 1090 uint32_t page_protection; 1091 }; 1092 1093 1094 struct mdp_mixer_info { 1095 int pndx; 1096 int pnum; 1097 int ptype; 1098 int mixer_num; 1099 int z_order; 1100 }; 1101 1102 #define MAX_PIPE_PER_MIXER 7 1103 1104 struct msmfb_mixer_info_req { 1105 int mixer_num; 1106 int cnt; 1107 struct mdp_mixer_info info[MAX_PIPE_PER_MIXER]; 1108 }; 1109 1110 enum { 1111 DISPLAY_SUBSYSTEM_ID, 1112 ROTATOR_SUBSYSTEM_ID, 1113 }; 1114 1115 enum { 1116 MDP_IOMMU_DOMAIN_CP, 1117 MDP_IOMMU_DOMAIN_NS, 1118 }; 1119 1120 enum { 1121 MDP_WRITEBACK_MIRROR_OFF, 1122 MDP_WRITEBACK_MIRROR_ON, 1123 MDP_WRITEBACK_MIRROR_PAUSE, 1124 MDP_WRITEBACK_MIRROR_RESUME, 1125 }; 1126 #endif /*_UAPI_MSM_MDP_H_*/ 1127
