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    Searched refs:isPPC64 (Results 1 - 15 of 15) sorted by null

  /external/llvm/lib/Target/PowerPC/
PPCFrameLowering.cpp 42 return STI.isPPC64() ? 16 : 8;
44 return STI.isPPC64() ? 16 : 4;
58 return STI.isPPC64() ? -8U : -4U;
61 return STI.isPPC64() ? -8U : -4U;
65 if (STI.isDarwinABI() || STI.isPPC64())
66 return (STI.isELFv2ABI() ? 4 : 6) * (STI.isPPC64() ? 8 : 4);
74 return STI.isPPC64() ? -16U : -8U;
77 return STI.isPPC64()
98 if (Subtarget.isPPC64()) {
238 if (Subtarget.isPPC64()) {
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PPCAsmPrinter.cpp 464 ((Subtarget->isPPC64() && MI->getOperand(0).getReg() == PPC::X3) ||
465 (!Subtarget->isPPC64() && MI->getOperand(0).getReg() == PPC::R3)) &&
468 ((Subtarget->isPPC64() && MI->getOperand(1).getReg() == PPC::X3) ||
469 (!Subtarget->isPPC64() && MI->getOperand(1).getReg() == PPC::R3)) &&
472 if (!Subtarget->isPPC64() && !Subtarget->isDarwin() &&
482 MCInstBuilder(Subtarget->isPPC64() ?
493 bool isPPC64 = Subtarget->isPPC64();
771 assert(Subtarget->isPPC64() && "Not supported for 32-bit PowerPC");
790 TmpInst.setOpcode(isPPC64 ? PPC::LD : PPC::LWZ)
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PPCSubtarget.cpp 53 IsPPC64(TargetTriple.getArch() == Triple::ppc64 ||
127 if (IsPPC64 && has64BitSupport())
189 CriticalPathRCs.push_back(isPPC64() ?
245 bool PPCSubtarget::isPPC64() const { return TM.isPPC64(); }
PPCRegisterInfo.cpp 61 : PPCGenRegisterInfo(TM.isPPC64() ? PPC::LR8 : PPC::LR,
62 TM.isPPC64() ? 0 : 1,
63 TM.isPPC64() ? 0 : 1),
91 if (TM.isPPC64())
96 if (TM.isPPC64())
113 return TM.isPPC64()
122 return TM.isPPC64()
144 return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_Darwin64_Altivec_RegMask
149 return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR464_Altivec_RegMask
205 if (TM.isPPC64()) {
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PPCTargetMachine.h 54 bool isPPC64() const {
PPCInstrInfo.cpp 449 bool isPPC64 = Subtarget.isPPC64();
501 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
512 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
570 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
584 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
646 bool isPPC64 = Subtarget.isPPC64();
654 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
655 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB)
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PPCISelLowering.cpp 66 bool isPPC64 = Subtarget.isPPC64();
67 setMinStackArgumentAlignment(isPPC64 ? 8:4);
103 if (isPPC64 || Subtarget.hasFPCVT()) {
106 isPPC64 ? MVT::i64 : MVT::i32);
109 isPPC64 ? MVT::i64 : MVT::i32);
306 if (isPPC64) {
325 if (Subtarget.isSVR4ABI() && !isPPC64)
370 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
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PPCSubtarget.h 87 bool IsPPC64;
187 /// isPPC64 - Return true if we are generating code for 64-bit pointer mode.
189 bool isPPC64() const;
PPCTLSDynamicCall.cpp 55 bool Is64Bit = MBB.getParent()->getSubtarget<PPCSubtarget>().isPPC64();
PPCTargetTransformInfo.cpp 168 if (ST->isPPC64() &&
227 if (ST->isPPC64())
PPCISelDAGToDAG.cpp     [all...]
PPCFastISel.cpp     [all...]
  /external/llvm/lib/Target/PowerPC/MCTargetDesc/
PPCMCTargetDesc.cpp 55 bool isPPC64 =
57 unsigned Flavour = isPPC64 ? 0 : 1;
58 unsigned RA = isPPC64 ? PPC::LR8 : PPC::LR;
72 bool isPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
77 MAI = new PPCMCAsmInfoDarwin(isPPC64, TheTriple);
79 MAI = new PPCELFMCAsmInfo(isPPC64, TheTriple);
82 unsigned Reg = isPPC64 ? PPC::X1 : PPC::R1;
PPCMCCodeEmitter.cpp 313 bool isPPC64 = TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le;
314 return CTX.getRegisterInfo()->getEncodingValue(isPPC64 ? PPC::X13 : PPC::R2);
  /external/llvm/lib/Target/PowerPC/AsmParser/
PPCAsmParser.cpp 247 bool IsPPC64;
253 bool isPPC64() const { return IsPPC64; }
298 IsPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
330 bool IsPPC64;
363 IsPPC64 = o.IsPPC64;
387 /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
388 bool isPPC64() const { return IsPPC64; }
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