| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64MCTargetDesc.cpp | 1 //===-- AArch64MCTargetDesc.cpp - AArch64 Target Descriptions ---*- C++ -*-===//
10 // This file provides AArch64 specific target descriptions.
53 InitAArch64MCRegisterInfo(X, AArch64::LR);
68 unsigned Reg = MRI.getDwarfRegNum(AArch64::SP, true);
91 "Only small and large code models are allowed on AArch64");
93 // AArch64 Darwin is always PIC.
|
| AArch64ELFStreamer.cpp | 1 //===- lib/MC/AArch64ELFStreamer.cpp - ELF Object Output for AArch64 ------===//
10 // This file assembles .s files and emits AArch64 ELF .o object files. Different
76 /// AArch64 ELF ABI:
121 /// AArch64 streamer overrides it to add the appropriate mapping symbol ($d)
129 /// AArch64 streamer overrides it to add the appropriate mapping symbol ($d)
|
| /hardware/invensense/6515/libsensors_iio/software/build/android/ |
| common.mk | 60 #--yd ANDROID_LINK_EXECUTABLE += -Wl,-T,$(ANDROID_ROOT)/prebuilts/gcc/linux-x86/aarch64/aarch64-linux-android-4.9/aarch64-linux-android/lib/ldscripts/armelf.x
62 ANDROID_LINK_EXECUTABLE += -Wl,-T,$(ANDROID_ROOT)/prebuilts/gcc/linux-x86/aarch64/aarch64-linux-android-4.9/aarch64-linux-android/lib/ldscripts/aarch64linux.x
|
| /toolchain/binutils/binutils-2.25/gold/ |
| aarch64-reloc-property.h | 0 // aarch64-reloc-property.h -- AArch64 relocation properties -*- C++ -*-
29 #include"aarch64.h"
50 RC_AARCH64, // Static AArch64 relocations
128 // Return portions of x as is defined in aarch64-reloc.def.
216 // Map aarch64 rtypes into range(0,300) as following
|
| aarch64-reloc-property.cc | 0 // aarch64-reloc-property.cc -- AArch64 relocation properties -*- C++ -*-
25 #include "aarch64-reloc-property.h"
26 #include "aarch64.h"
123 #include"aarch64-reloc.def"
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64RegisterInfo.td | 1 //=- AArch64RegisterInfo.td - Describe the AArch64 Regisers --*- tablegen -*-=//
18 let Namespace = "AArch64";
22 let Namespace = "AArch64" in {
47 let Namespace = "AArch64" in {
130 def GPR32common : RegisterClass<"AArch64", [i32], 32, (sequence "W%u", 0, 30)> {
134 def GPR64common : RegisterClass<"AArch64", [i64], 64,
140 def GPR32 : RegisterClass<"AArch64", [i32], 32, (add GPR32common, WZR)> {
144 def GPR64 : RegisterClass<"AArch64", [i64], 64, (add GPR64common, XZR)> {
150 def GPR32sp : RegisterClass<"AArch64", [i32], 32, (add GPR32common, WSP)> {
154 def GPR64sp : RegisterClass<"AArch64", [i64], 64, (add GPR64common, SP)>
[all...] |
| AArch64CleanupLocalDynamicTLSPass.cpp | 25 #include "AArch64.h"
65 case AArch64::TLSDESC_CALLSEQ:
101 AArch64::X0).addReg(TLSBaseAddrReg);
117 *TLSBaseAddrReg = RegInfo.createVirtualRegister(&AArch64::GPR64RegClass);
123 .addReg(AArch64::X0);
|
| AArch64Subtarget.cpp | 1 //===-- AArch64Subtarget.cpp - AArch64 Subtarget Information ----*- C++ -*-===//
10 // This file implements the AArch64 specific subclass of TargetSubtarget.
24 #define DEBUG_TYPE "aarch64-subtarget"
31 EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if "
36 UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of "
|
| /external/llvm/test/Transforms/InstCombine/ |
| 2012-04-23-Neon-Intrinsics.ll | 71 %a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %x, <4 x i16> zeroinitializer) nounwind
79 %a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %x, <4 x i16> <i16 1, i16 1, i16 1, i16 1>) nounwind
88 %a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> <i16 3, i16 3, i16 3, i16 3>, <4 x i16> <i16 2, i16 2, i16 2, i16 2>) nounwind
96 %b = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>, <4 x i16> <i16 1, i16 1, i16 1, i16 1>) nounwind
104 %b = tail call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>, <4 x i16> <i16 1, i16 1, i16 1, i16 1>) nounwind
112 %a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> <i16 2, i16 2, i16 2, i16 2>, <4 x i16> %x) nounwind
116 ; CHECK-NEXT: %a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> <i16 2, i16 2, i16 2, i16 2>, <4 x i16> %x) [[NUW:#[0-9]+]]
122 %a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> <i16 3, i16 3, i16 3, i16 3>, <4 x i16> <i16 2, i16 2, i16 2, i16 2>) nounwind
130 declare <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
131 declare <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16>, <4 x i16>) nounwind readnon
[all...] |
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | 1 //==- AArch64AsmParser.cpp - Parse AArch64 assembly to MCInst instructions -==//
146 /// AArch64Operand - Instances of this class represent a parsed AArch64 machine
924 AArch64MCRegisterClasses[AArch64::FPR128_loRegClassID].contains(
929 AArch64MCRegisterClasses[AArch64::GPR64RegClassID].contains(Reg.RegNum);
933 AArch64MCRegisterClasses[AArch64::WSeqPairsClassRegClassID].contains(
938 AArch64MCRegisterClasses[AArch64::XSeqPairsClassRegClassID].contains(
944 AArch64MCRegisterClasses[AArch64::GPR64spRegClassID].contains(Reg.RegNum);
[all...] |
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-neon-2velem-high.ll | 15 %vmull15.i.i = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> %vecinit3.i.i)
26 %vmull15.i.i = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> <i16 29, i16 29, i16 29, i16 29>)
39 %vmull9.i.i = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> %vecinit1.i.i)
50 %vmull9.i.i = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> <i32 511, i32 511>)
65 %vmull15.i.i = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> %vecinit3.i.i)
76 %vmull15.i.i = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> <i16 4352, i16 4352, i16 4352, i16 4352>)
89 %vmull9.i.i = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> %vecinit1.i.i)
100 %vmull9.i.i = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> <i32 4294966784, i32 4294966784>)
115 %vqdmull15.i.i = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> %vecinit3.i.i)
126 %vqdmull15.i.i = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> <i16 61183, i16 61183, i16 61183, i16 61183>
[all...] |
| arm64-vecCmpBr.ll | 1 ; RUN: llc -march=arm64 -aarch64-neon-syntax=apple < %s -mcpu=cyclone | FileCheck %s
16 %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8> %0) #3
42 %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8> %0) #3
66 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %0) #3
89 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8> %0) #3
112 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %0) #3
135 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8> %0) #3
158 %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8> %0) #3
181 %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8> %0) #3
195 declare i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8>) #
[all...] |
| arm64-vbitwise.ll | 1 ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
7 %tmp3 = call <8 x i8> @llvm.aarch64.neon.rbit.v8i8(<8 x i8> %tmp1)
15 %tmp3 = call <16 x i8> @llvm.aarch64.neon.rbit.v16i8(<16 x i8> %tmp1)
19 declare <8 x i8> @llvm.aarch64.neon.rbit.v8i8(<8 x i8>) nounwind readnone
20 declare <16 x i8> @llvm.aarch64.neon.rbit.v16i8(<16 x i8>) nounwind readnone
|
| arm64-vsub.ll | 1 ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
8 %tmp3 = call <8 x i8> @llvm.aarch64.neon.subhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
17 %tmp3 = call <4 x i16> @llvm.aarch64.neon.subhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)
26 %tmp3 = call <2 x i32> @llvm.aarch64.neon.subhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2)
34 %vsubhn2.i = tail call <8 x i8> @llvm.aarch64.neon.subhn.v8i8(<8 x i16> %a, <8 x i16> %b) nounwind
35 %vsubhn_high2.i = tail call <8 x i8> @llvm.aarch64.neon.subhn.v8i8(<8 x i16> %a, <8 x i16> %b) nounwind
44 %vsubhn2.i = tail call <4 x i16> @llvm.aarch64.neon.subhn.v4i16(<4 x i32> %a, <4 x i32> %b) nounwind
45 %vsubhn_high3.i = tail call <4 x i16> @llvm.aarch64.neon.subhn.v4i16(<4 x i32> %a, <4 x i32> %b) nounwind
54 %vsubhn2.i = tail call <2 x i32> @llvm.aarch64.neon.subhn.v2i32(<2 x i64> %a, <2 x i64> %b) nounwind
55 %vsubhn_high3.i = tail call <2 x i32> @llvm.aarch64.neon.subhn.v2i32(<2 x i64> %a, <2 x i64> %b) nounwin
[all...] |
| arm64-neon-2velem.ll | 3 declare <2 x double> @llvm.aarch64.neon.fmulx.v2f64(<2 x double>, <2 x double>)
5 declare <4 x float> @llvm.aarch64.neon.fmulx.v4f32(<4 x float>, <4 x float>)
7 declare <2 x float> @llvm.aarch64.neon.fmulx.v2f32(<2 x float>, <2 x float>)
9 declare <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32>, <4 x i32>)
11 declare <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32>, <2 x i32>)
13 declare <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16>, <8 x i16>)
15 declare <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16>, <4 x i16>)
17 declare <4 x i32> @llvm.aarch64.neon.sqdmulh.v4i32(<4 x i32>, <4 x i32>)
19 declare <2 x i32> @llvm.aarch64.neon.sqdmulh.v2i32(<2 x i32>, <2 x i32>)
21 declare <8 x i16> @llvm.aarch64.neon.sqdmulh.v8i16(<8 x i16>, <8 x i16>
[all...] |
| arm64-neon-3vdiff.ll | 3 declare <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8>, <8 x i8>)
5 declare <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32>, <2 x i32>)
7 declare <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64>, <2 x i64>)
9 declare <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16>, <4 x i16>)
11 declare <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32>, <4 x i32>)
13 declare <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64>, <2 x i64>)
15 declare <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32>, <4 x i32>)
17 declare <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32>, <2 x i32>)
19 declare <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16>, <4 x i16>)
21 declare <8 x i16> @llvm.aarch64.neon.umull.v8i16(<8 x i8>, <8 x i8>
[all...] |
| /toolchain/binutils/binutils-2.25/ |
| README.google | 41 gas/testsuite/gas/aarch64/mapmisc.d
91 gold/aarch64.cc
105 gold/aarch64.cc
112 gold/aarch64.cc
136 gold/aarch64-reloc.def
137 gold/aarch64.cc
184 gold/aarch64-reloc.def
185 gold/aarch64.cc
188 Add support to 2 AARCH64 TLSLD relocations. Change _TLS_MODULE_BASE_.
|
| /external/vixl/tools/ |
| make_instruction_doc.pl | 32 # Extra pseudo instructions added to AArch64.
75 This is a list of the AArch64 instructions supported by the VIXL assembler,
77 operations to the precision required by AArch64 - please check the simulator
82 print describe_insts('AArch64 integer instructions', 'integer');
83 print describe_insts('AArch64 floating point and NEON instructions', 'float');
|
| /frameworks/compile/mclinker/lib/Target/AArch64/ |
| AArch64LDBackend.h | 25 /// AArch64GNULDBackend - linker backend of AArch64 target of GNU ELF format
103 /// getTargetSectionOrder - compute the layout order of AArch64 target
168 // LDSection* m_pPreemptMap; // .AArch64.preemptmap
169 // LDSection* m_pDebugOverlay; // .AArch64.debug_overlay
170 // LDSection* m_pOverlayTable; // .AArch64.overlay_table
|
| /toolchain/binutils/binutils-2.25/gas/config/ |
| tc-aarch64.h | 1 /* tc-aarch64.h -- Header file for tc-aarch64.c.
24 #include "opcode/aarch64.h"
70 #define md_convert_frag(b,s,f) as_fatal ("aarch64 convert_frag called\n")
99 #define LISTING_HEADER "AARCH64 GAS "
|
| /toolchain/binutils/binutils-2.25/ld/testsuite/ |
| ChangeLog-2012 | 72 * lib/ld-lib.exp (check_shared_lib_support): Add aarch64*-*-elf and
485 * ld-aarch64/tlsle-symbol-offset.s: New file.
486 * ld-aarch64/tlsle-symbol-offset.d: New file.
487 * ld-aarch64/aarch64-elf.exp: Add tlsle-symbol-offset test.
496 * ld-aarch64/emit-relocs-309-low.d: Replace symbol with regexp.
497 * ld-aarch64/emit-relocs-309-up.d: Likewise.
537 * ld-aarch64/aarch64-elf.exp: New reloc tests.
538 * ld-aarch64/emit-relocs-309-low-bad.d: New file. Expected asm for tes
[all...] |
| /toolchain/binutils/binutils-2.25/opcodes/po/ |
| opcodes.pot | 22 #: aarch64-dis.c:81 arm-dis.c:4606
27 #: aarch64-dis.c:2395
31 "The following AARCH64 specific disassembler options are supported for use\n"
35 #: aarch64-dis.c:2399
42 #: aarch64-dis.c:2402
49 #: aarch64-dis.c:2406
56 #: aarch64-dis.c:2410 mips-dis.c:2231 mips-dis.c:2239 mips-dis.c:2241
61 #: aarch64-opc.c:1152
65 #: aarch64-opc.c:1162
69 #: aarch64-opc.c:117
[all...] |
| /bionic/tests/ |
| __cxa_thread_atexit_test.cpp | 39 // b/25642296, aarch64 clang compiled "thread_local" does not link.
57 << "thread_local does not work with aarch64 clang/llvm.\n";
80 << "thread_local does not work with aarch64 clang/llvm.\n";
|
| /build/soong/cc/ |
| arm64_device.go | 85 "prebuilts/gcc/${HostPrebuiltTag}/aarch64/aarch64-linux-android-${arm64GccVersion}")
87 pctx.StaticVariable("arm64GccTriple", "aarch64-linux-android")
|
| /external/libunwind/ |
| Android.build.mk | 109 # Translate arm64 to aarch64 in c includes and src files.
111 $(subst tdep-arm64,tdep-aarch64,$(LOCAL_C_INCLUDES_arm64))
114 $(subst src/arm64,src/aarch64,$(LOCAL_SRC_FILES_arm64))
|
