| /external/llvm/test/CodeGen/AArch64/ |
| concat_vector-truncated-scalar-combine.ll | 3 target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
|
| inline-asm-globaladdress.ll | 4 target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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| memcpy-f128.ll | 3 %structA = type { i128 }
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| paired-load.ll | 2 target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
|
| dp-3source.ll | 77 %ext1 = sext i64 %lhs to i128
78 %ext2 = sext i64 %rhs to i128
79 %res = mul i128 %ext1, %ext2
80 %high = lshr i128 %res, 64
81 %val = trunc i128 %high to i64
88 %ext1 = zext i64 %lhs to i128
89 %ext2 = zext i64 %rhs to i128
90 %res = mul i128 %ext1, %ext2
91 %high = lshr i128 %res, 64
92 %val = trunc i128 %high to i6
[all...] |
| arm64-aapcs.ll | 6 define i128 @test_i128_align(i32, i128 %arg, i32 %after) {
10 ret i128 %arg
100 ; We weren't marking x7 as used after deciding that the i128 didn't fit into
103 define i128 @test_i128_shadow([7 x i64] %x0_x6, i128 %sp) {
107 ret i128 %sp
|
| /external/llvm/test/CodeGen/X86/ |
| complex-asm.ll | 9 call void asm sideeffect "", "=*r,r,r,0,~{dirflag},~{fpsr},~{flags}"(%0* %v, i32 0, i32 1, i128 undef) nounwind
|
| 2012-09-13-dagco-fneg.ll | 15 %0 = bitcast <4 x float> %tmp44.i to i128
16 %1 = zext i128 %0 to i512
|
| pr12312.ll | 6 %0 = bitcast <4 x i32> %input to i128
7 %1 = icmp ne i128 %0, 0
65 %0 = bitcast <4 x i32> %input to i128
66 %1 = icmp ne i128 %0, 0
112 %0 = bitcast <4 x i32> %input to i128
113 %1 = icmp ne i128 %0, 0
|
| fp128-cast.ll | 203 %0 = bitcast fp128 %mul to i128
204 %shift = lshr i128 %0, 32
205 %or5 = or i128 %shift, %0
206 %or = trunc i128 %or5 to i32
240 %conv = zext i64 %a to i128
241 %shl = shl nuw i128 %conv, 64
242 %conv1 = zext i64 %b to i128
243 %or = or i128 %shl, %conv1
244 %add = add i128 %or, 3
245 %0 = bitcast i128 %add to fp12
[all...] |
| /external/llvm/test/DebugInfo/AArch64/ |
| big-endian-dump.ll | 5 target datalayout = "E-m:e-i64:64-i128:128-n32:64-S128"
|
| little-endian-dump.ll | 5 target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
|
| /external/llvm/test/Instrumentation/DataFlowSanitizer/ |
| external_mask.ll | 2 target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
|
| /frameworks/rs/driver/runtime/ll64/ |
| math.ll | 1 target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
|
| /external/bouncycastle/bcprov/src/main/java/org/bouncycastle/jcajce/provider/asymmetric/util/ |
| BaseAgreementSpi.java | 48 Integer i128 = Integers.valueOf(128); typedefs
54 keySizes.put("BLOWFISH", i128);
57 keySizes.put(NISTObjectIdentifiers.id_aes128_ECB.getId(), i128); typedefs
60 keySizes.put(NISTObjectIdentifiers.id_aes128_CBC.getId(), i128); typedefs
63 keySizes.put(NISTObjectIdentifiers.id_aes128_CFB.getId(), i128); typedefs
66 keySizes.put(NISTObjectIdentifiers.id_aes128_OFB.getId(), i128); typedefs
69 keySizes.put(NISTObjectIdentifiers.id_aes128_wrap.getId(), i128); typedefs
72 keySizes.put(NISTObjectIdentifiers.id_aes128_CCM.getId(), i128); typedefs
75 keySizes.put(NISTObjectIdentifiers.id_aes128_GCM.getId(), i128); typedefs
78 keySizes.put(NTTObjectIdentifiers.id_camellia128_wrap.getId(), i128); typedefs
81 keySizes.put(KISAObjectIdentifiers.id_npki_app_cmsSeed_wrap.getId(), i128); typedefs
[all...] |
| /external/llvm/test/CodeGen/ARM/ |
| 2012-01-26-CopyPropKills.ll | 81 %tmp63 = bitcast <4 x float> %tmp46 to i128
82 %tmp64 = bitcast <4 x float> %tmp54 to i128
83 %tmp65 = bitcast <4 x float> %tmp61 to i128
84 %tmp66 = lshr i128 %tmp63, 64
85 %tmp67 = trunc i128 %tmp66 to i64
88 %tmp70 = lshr i128 %tmp64, 64
89 %tmp71 = trunc i128 %tmp70 to i64
91 %tmp73 = trunc i128 %tmp65 to i64
101 %tmp82 = trunc i512 %tmp80 to i128
102 %tmp83 = trunc i512 %tmp81 to i128
[all...] |
| /external/clang/test/Analysis/ |
| builtin_signbit.cpp | 11 // CHECK: i128
32 // CHECK: i128
|
| /external/clang/test/CodeGen/ |
| aarch64-type-sizes.c | 4 // CHECK-LE: target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
5 // CHECK-BE: target datalayout = "E-m:e-i64:64-i128:128-n32:64-S128"
|
| builtins-arm-exclusive.c | 319 // CHECK-ARM64: [[ADDR8:%.*]] = bitcast i128* %addr to i8*
323 // CHECK-ARM64: [[RESHI64:%.*]] = zext i64 [[RESHI]] to i128
324 // CHECK-ARM64: [[RESLO64:%.*]] = zext i64 [[RESLO]] to i128
325 // CHECK-ARM64: [[RESHIHI:%.*]] = shl nuw i128 [[RESHI64]], 64
326 // CHECK-ARM64: [[INTRES:%.*]] = or i128 [[RESHIHI]], [[RESLO64]]
327 // CHECK-ARM64: ret i128 [[INTRES]]
334 // CHECK-ARM64: [[VALLO:%.*]] = trunc i128 %val to i64
335 // CHECK-ARM64: [[VALHI128:%.*]] = lshr i128 %val, 64
336 // CHECK-ARM64: [[VALHI:%.*]] = trunc i128 [[VALHI128]] to i64
337 // CHECK-ARM64: [[ADDR8:%.*]] = bitcast i128* %addr to i8
[all...] |
| /external/llvm/test/CodeGen/Generic/ |
| 2009-03-17-LSR-APInt.ll | 53 %indvar = phi i128 [ %indvar.next144, %bb47 ], [ 0, %entry ] ; <i128> [#uses=2]
57 %tmp = shl i128 %indvar, 64 ; <i128> [#uses=1]
58 %tmp96 = and i128 %tmp, 79228162495817593519834398720 ; <i128> [#uses=0]
62 %indvar.next144 = add i128 %indvar, 1 ; <i128> [#uses=1]
|
| /external/llvm/test/Instrumentation/MemorySanitizer/ |
| vector_shift.ll | 46 ; CHECK: = sext i1 {{.*}} to i128
47 ; CHECK: = bitcast i128 {{.*}} to <8 x i16>
61 ; CHECK: = bitcast <8 x i16> {{.*}} to i128
62 ; CHECK: = trunc i128 {{.*}} to i64
64 ; CHECK: = sext i1 {{.*}} to i128
65 ; CHECK: = bitcast i128 {{.*}} to <8 x i16>
|
| /external/llvm/test/Transforms/NaryReassociate/NVPTX/ |
| nary-gep.ll | 111 define void @reassociate_gep_128(float* %a, i128 %i, i128 %j) {
113 %1 = add i128 %i, %j
114 %2 = getelementptr float, float* %a, i128 %i
115 ; CHECK: [[t1:[^ ]+]] = getelementptr float, float* %a, i128 %i
118 %3 = getelementptr float, float* %a, i128 %1
119 ; CHECK: [[truncj:[^ ]+]] = trunc i128 %j to i64
|
| /external/clang/test/OpenMP/ |
| atomic_read_codegen.c | 135 // CHECK: [[LD:%.+]] = load atomic i128, i128* bitcast (x86_fp80*
136 // CHECK: [[BITCAST:%.+]] = bitcast x86_fp80* [[LDTEMP:%.*]] to i128*
137 // CHECK: store i128 [[LD]], i128* [[BITCAST]]
200 // CHECK: load atomic i128, i128*
231 // CHECK: [[I128VAL:%.+]] = load atomic i128, i128* bitcast (<4 x i32>* @{{.+}} to i128*) monotoni
[all...] |
| /external/llvm/test/CodeGen/Mips/llvm-ir/ |
| and.ll | 84 define signext i128 @and_i128(i128 signext %a, i128 signext %b) {
100 %r = and i128 %a, %b
101 ret i128 %r
|
| or.ll | 85 define signext i128 @or_i128(i128 signext %a, i128 signext %b) {
101 %r = or i128 %a, %b
102 ret i128 %r
|
