| /external/llvm/test/CodeGen/PowerPC/ |
| mcm-13.ll | 21 ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha
22 ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]])
|
| mcm-6.ll | 21 ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha
22 ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]])
|
| mcm-7.ll | 22 ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha
23 ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]])
|
| mcm-8.ll | 20 ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha
21 ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]])
|
| mcm-9.ll | 21 ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha
22 ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]])
|
| mcm-default.ll | 20 ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha
21 ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]])
|
| tls-store2.ll | 33 ; CHECK: mr [[REG1:[0-9]+]], 3
34 ; CHECK: std {{[0-9]+}}, 0([[REG1]])
|
| anon_aggr.ll | 32 ; DARWIN32: mr r[[REG1:[0-9]+]], r[[REGA:[0-9]+]]
35 ; DARWIN32: stw r[[REG1]], -[[OFFSET1:[0-9]+]]
42 ; DARWIN64: mr r[[REG1:[0-9]+]], r[[REGA:[0-9]+]]
45 ; DARWIN64: std r[[REG1]], -[[OFFSET1:[0-9]+]]
73 ; DARWIN32: addi r[[REG1:[0-9]+]], r[[REGSP:[0-9]+]], 36
118 ; DARWIN32: addi r[[REG1:[0-9]+]], r[[REGSP:[0-9]+]], 36
164 ; DARWIN32: addi r[[REG1:[0-9]+]], r1, 100
170 ; DARWIN32: lwz r[[REG1]], -[[OFFSET1]]
171 ; DARWIN32: lwz r[[REG1]], -[[OFFSET2]]
|
| htm.ll | 80 ; CHECK: mtspr 130, [[REG1:[0-9]+]]
91 ; CHECK: mfspr [[REG1:[0-9]+]], 130
99 ; CHECK: mfspr [[REG1:[0-9]+]], 131
107 ; CHECK: mfspr [[REG1:[0-9]+]], 128
115 ; CHECK: mfspr [[REG1:[0-9]+]], 129
|
| /external/llvm/test/CodeGen/SystemZ/ |
| vec-args-02.ll | 19 ; CHECK-STACK-DAG: vrepif [[REG1:%v[0-9]+]], 3
20 ; CHECK-STACK-DAG: vst [[REG1]], 160(%r15)
|
| vec-args-05.ll | 22 ; CHECK-STACK-DAG: larl [[REG1:%r[0-9]+]], .LCPI0_0
23 ; CHECK-STACK-DAG: vl [[VREG:%v[0-9]+]], 0([[REG1]])
|
| vec-move-17.ll | 24 ; CHECK: vpkh [[REG1:%v[0-9]+]], %v24, %v24
25 ; CHECK: vsteg [[REG1]], 0(%r2)
55 ; CHECK: vpkf [[REG1:%v[0-9]+]], %v24, %v24
56 ; CHECK: vsteg [[REG1]], 0(%r2)
98 ; CHECK: vpkg [[REG1:%v[0-9]+]], %v24, %v24
99 ; CHECK: vsteg [[REG1]], 0(%r2)
|
| alloca-01.ll | 25 ; CHECK-DAG: la [[REG1:%r[0-5]]], 7(%r2)
26 ; CHECK-DAG: nill [[REG1]], 65528
28 ; CHECK: sgr [[REG2]], [[REG1]]
|
| /external/webrtc/webrtc/system_wrappers/include/ |
| asm_defines.h | 59 .macro streqh reg1, reg2, num
60 strheq \reg1, \reg2, \num variable
|
| /external/llvm/test/CodeGen/X86/ |
| half.ll | 86 ; CHECK-F16C-NEXT: vmovd [[REG0]], [[REG1:%[a-z0-9]+]]
87 ; CHECK-F16C-NEXT: vcvtph2ps [[REG1]], [[REG2:%[a-z0-9]+]]
123 ; CHECK-LIBCALL-NEXT: movss {{.[A-Z_0-9]+}}(%rip), [[REG1:%[a-z0-9]+]]
125 ; CHECK-LIBCALL-NEXT: subss [[REG1]], [[REG2]]
130 ; CHECK-LIBCALL-NEXT: ucomiss [[REG1]], %xmm0
136 ; CHECK-F16C-NEXT: vmovd [[REG0]], [[REG1:%[a-z0-9]+]]
137 ; CHECK-F16C-NEXT: vcvtph2ps [[REG1]], [[REG2:%[a-z0-9]+]]
162 ; CHECK-LIBCALL-NEXT: cvtsi2ssq %rdi, [[REG1:%[a-z0-9]+]]
163 ; CHECK-F16C-NEXT: vcvtsi2ssq %rdi, [[REG1:%[a-z0-9]+]], [[REG1]]
[all...] |
| /external/boringssl/src/crypto/perlasm/ |
| x86gas.pl | 70 { my($addr,$reg1,$reg2,$idx)=@_;
73 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
79 $reg1 = "%$reg1" if ($reg1);
86 $ret .= "($reg1,$reg2,$idx)";
88 elsif ($reg1)
89 { $ret .= "($reg1)"; }
|
| x86masm.pl | 39 { my($size,$addr,$reg1,$reg2,$idx)=@_;
42 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
61 $ret .= "+$reg1" if ($reg1 ne "");
64 { $ret .= "$reg1"; }
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| schedule-fs-loop-nested-if.ll | 4 define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #1 {
6 %0 = extractelement <4 x float> %reg1, i32 0
7 %1 = extractelement <4 x float> %reg1, i32 1
8 %2 = extractelement <4 x float> %reg1, i32 2
9 %3 = extractelement <4 x float> %reg1, i32 3
|
| /external/llvm/test/CodeGen/ARM/ |
| big-endian-vector-callee.ll | 582 ; SOFT: vmov [[REG1:d[0-9]+]], r3, r2
584 ; SOFT: vadd.f64 d{{[0-9]+}}, [[REG1]]
598 ; SOFT: vmov [[REG1:d[0-9]+]], r3, r2
655 ; CHECK: vmov.32 [[REG1:d[0-9]+]][0], r0
656 ; CHECK: vmov.32 [[REG1]][1], r1
663 ; SOFT: vadd.f64 [[REG1:d[0-9]+]]
666 ; SOFT: vmov r3, r2, [[REG1]]
673 ; SOFT: vmov [[REG1:d[0-9]+]], r3, r2
680 ; SOFT: vadd.f64 [[REG1:d[0-9]+]]
683 ; SOFT: vmov r3, r2, [[REG1]]
[all...] |
| arm-modifier.ll | 49 ; CHECK: stm {{lr|r[0-9]+}}, {[[REG1:(r[0-9]+)]], r{{[0-9]+}}}
50 ; CHECK: adds {{lr|r[0-9]+}}, [[REG1]]
64 ;CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
|
| dyn-stackalloc.ll | 18 ; CHECK: bic [[REG1:r[0-9]+]],
19 ; CHECK-NOT: sub r{{[0-9]+}}, sp, [[REG1]]
20 ; CHECK: sub sp, sp, [[REG1]]
|
| fast-isel-pic.ll | 19 ; ARM: ldr [[reg1:r[0-9]+]],
20 ; ARM: add [[reg1]], pc, [[reg1]]
|
| /external/libunwind/src/ptrace/ |
| _UPT_access_mem.c | 63 long reg1, reg2;
64 reg1 = ptrace (PTRACE_PEEKDATA, pid, (void*) (uintptr_t) addr, 0);
70 *val = ((unw_word_t)(reg2) << 32) | (uint32_t) reg1;
|
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-vshr.ll | 5 ; CHECK: neg.8h [[REG1:v[0-9]+]], [[REG1]]
6 ; CHECK-NEXT: sshl.8h [[REG2:v[0-9]+]], [[REG2]], [[REG1]]
|
| /hardware/bsp/intel/peripheral/libupm/src/h3lis331dl/ |
| h3lis331dl.cxx | 81 uint8_t reg1 = m_i2c.readReg(REG_REG1); local
83 reg1 &= ~(REG1_DR0 | REG1_DR1);
84 reg1 |= (odr << REG1_DR_SHIFT);
86 if (m_i2c.writeReg(REG_REG1, reg1))
98 uint8_t reg1 = m_i2c.readReg(REG_REG1); local
100 reg1 &= ~(REG1_PM0 | REG1_PM1 | REG1_PM2);
101 reg1 |= (pm << REG1_PM_SHIFT);
103 if (m_i2c.writeReg(REG_REG1, reg1))
115 uint8_t reg1 = m_i2c.readReg(REG_REG1); local
117 reg1 &= ~(REG1_XEN | REG1_YEN | REG1_ZEN)
[all...] |
