| /external/llvm/test/CodeGen/PowerPC/ |
| stack-realign.ll | 115 ; CHECK-DAG: lis [[REG1:[0-9]+]], -13
118 ; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 51808
131 ; CHECK-32-DAG: lis [[REG1:[0-9]+]], -13
134 ; CHECK-32-DAG: ori [[REG2:[0-9]+]], [[REG1]], 51904
145 ; CHECK-32-PIC-DAG: lis [[REG1:[0-9]+]], -13
148 ; CHECK-32-PIC-DAG: ori [[REG2:[0-9]+]], [[REG1]], 51904
|
| mcm-5.ll | 55 ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha
56 ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]])
|
| no-rlwimi-trivial-commute.mir | 82 ; CHECK: %[[REG1:[0-9]+]] = LI 0
83 ; CHECK: %[[REG2:[0-9]+]] = COPY %[[REG1]]
|
| ppc64-byval-align.ll | 53 ; CHECK: addi [[REG1:[0-9]+]], 1, [[OFF]]
54 ; CHECK: lxvw4x [[REG2:[0-9]+]], 0, [[REG1]]
|
| ppc64le-aggregates.ll | 236 ; CHECK-DAG: lwz [[REG1:[0-9]+]], [[OFF1]](1)
239 ; CHECK-DAG: sldi [[REG1]], [[REG1]], 32
241 ; CHECK-DAG: or 9, [[REG0]], [[REG1]]
284 ; CHECK-DAG: lwz [[REG1:[0-9]+]], 4({{[0-9]+}})
285 ; CHECK-DAG: sldi [[REG2:[0-9]+]], [[REG1]], 32
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| llvm.pow.ll | 30 define void @test2(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 {
31 %vec = call <4 x float> @llvm.pow.v4f32( <4 x float> %reg0, <4 x float> %reg1)
|
| load-input-fold.ll | 3 define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3) #0 {
5 %0 = extractelement <4 x float> %reg1, i32 0
6 %1 = extractelement <4 x float> %reg1, i32 1
7 %2 = extractelement <4 x float> %reg1, i32 2
8 %3 = extractelement <4 x float> %reg1, i32 3
|
| schedule-vs-if-nested-loop.ll | 4 define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 {
6 %0 = extractelement <4 x float> %reg1, i32 0
7 %1 = extractelement <4 x float> %reg1, i32 1
8 %2 = extractelement <4 x float> %reg1, i32 2
9 %3 = extractelement <4 x float> %reg1, i32 3
|
| /external/llvm/test/CodeGen/ARM/ |
| fp16-args.ll | 37 ; HARD-NEXT: uxth [[REG1:r[0-9]+]], [[REG0]]
38 ; HARD-NEXT: vmov s0, [[REG1]]
|
| fpcmp-opt.ll | 36 ; CHECK: ldrd [[REG1:(r[0-9]+)]], [[REG2:(r[0-9]+)]], [r0]
39 ; CHECK: cmp [[REG1]], #0
|
| inlineasm-64bit.ll | 6 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
7 ; CHECK: strexd [[REG1]], {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
49 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
50 ; CHECK: strexd [[REG1]], {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
|
| /external/llvm/test/CodeGen/Mips/Fast-ISel/ |
| simplestorefp1.ll | 19 ; CHECK: lui $[[REG1:[0-9]+]], 16339
20 ; CHECK: ori $[[REG2:[0-9]+]], $[[REG1]], 46662
|
| /external/llvm/test/CodeGen/SystemZ/Large/ |
| spill-02.py | 7 # CHECK-DAG: stg [[REG1:%r[0-9]+]], 8168(%r15)
12 # CHECK-DAG: lg [[REG1]], 8168(%r15)
|
| /external/llvm/test/CodeGen/SystemZ/ |
| vec-args-01.ll | 30 ; CHECK-STACK-DAG: vrepif [[REG1:%v[0-9]+]], 9
31 ; CHECK-STACK-DAG: vst [[REG1]], 168(%r15)
|
| vec-args-04.ll | 35 ; CHECK-STACK-DAG: larl [[REG1:%r[0-9]+]], .LCPI0_0
36 ; CHECK-STACK-DAG: vl [[VREG0:%v[0-9]+]], 0([[REG1]])
|
| branch-06.ll | 153 ; CHECK-DAG: llc [[REG1:%r[0-5]]], 0(
155 ; CHECK: crjl [[REG1]], [[REG2]], .L[[LABEL]]
175 ; CHECK-DAG: llh [[REG1:%r[0-5]]], 0(
177 ; CHECK: crjl [[REG1]], [[REG2]], .L[[LABEL]]
|
| /external/llvm/test/CodeGen/X86/ |
| avoid_complex_am.ll | 4 ; On X86, reg1 + 1*reg2 has the same cost as reg1 + 8*reg2.
|
| mmx-fold-load.ll | 6 ; CHECK: movq (%[[REG1:[a-z]+]]), %mm0
23 ; CHECK: movq (%[[REG1]]), %mm0
40 ; CHECK: movq (%[[REG1]]), %mm0
57 ; CHECK: movq (%[[REG1]]), %mm0
74 ; CHECK: movq (%[[REG1]]), %mm0
91 ; CHECK: movq (%[[REG1]]), %mm0
108 ; CHECK: movq (%[[REG1]]), %mm0
125 ; CHECK: movq (%[[REG1]]), %mm0
|
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-patchpoint-webkit_jscc.ll | 50 ; FAST: orr [[REG1:x[0-9]+]], xzr, #0x2
53 ; FAST-NEXT: str [[REG1]], [sp, #-32]!
88 ; FAST: orr [[REG1:x[0-9]+]], xzr, #0x2
93 ; FAST-NEXT: str [[REG1]], [sp, #-64]!
|
| arm64-fast-isel-call.ll | 16 ; LARGE: ldr [[REG1:x[0-9]+]], {{\[}}[[REG0]], _call0@GOTPAGEOFF{{\]}}
17 ; LARGE-NEXT: blr [[REG1]]
82 ; CHECK: mov [[REG1:x[0-9]+]], xzr
88 ; CHECK: mov x0, [[REG1]]
239 ; CHECK: ubfx [[REG1:x[0-9]+]], {{x[0-9]+}}, #0, #32
241 ; CHECK: add {{x[0-9]+}}, [[REG1]], x1
|
| /external/skia/gm/ |
| complexclip_blur_tiled.cpp | 74 static GMRegistry reg1(MyFactory1);
|
| imageblurtiled.cpp | 78 static GMRegistry reg1(MyFactory1);
|
| /external/llvm/lib/Target/Mips/ |
| MipsAsmPrinter.h | 73 unsigned Reg1, unsigned Reg2);
76 unsigned Reg1, unsigned Reg2, unsigned Reg3);
79 unsigned Reg1, unsigned Reg2, unsigned FPReg1,
|
| Mips16InstrInfo.cpp | 265 unsigned Reg1, unsigned Reg2) const {
268 // li reg1, constant
270 // add reg1, reg1, reg2
271 // move sp, reg1
274 MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwConstant32), Reg1);
278 MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::AdduRxRyRz16), Reg1);
279 MIB3.addReg(Reg1);
283 MIB4.addReg(Reg1, RegState::Kill);
|
| /external/google-breakpad/src/common/ |
| dwarf_cfi_to_module_unittest.cc | 63 register_names.push_back("reg1");
248 expected_initial["reg0"] = "reg1";
260 expected_initial[".ra"] = "reg1";
275 expected_changes[entry_address + 1][".ra"] = "reg1";
|
