| /external/llvm/lib/Target/AMDGPU/ |
| SIFixSGPRCopies.cpp | 133 unsigned SrcReg = Copy.getOperand(1).getReg();
136 TargetRegisterInfo::isVirtualRegister(SrcReg) ?
137 MRI.getRegClass(SrcReg) :
138 TRI.getPhysRegClass(SrcReg);
217 unsigned SrcReg = MI.getOperand(I).getReg();
220 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
|
| AMDGPUInstrInfo.h | 51 bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
78 unsigned SrcReg, bool isKill, int FrameIndex,
190 unsigned DstReg, unsigned SrcReg) const = 0;
|
| SIInstrInfo.cpp | 314 unsigned DestReg, unsigned SrcReg,
320 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
367 assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
369 .addReg(SrcReg, getKillRegState(KillSrc));
374 if (AMDGPU::SReg_64RegClass.contains(SrcReg)) {
376 .addReg(SrcReg, getKillRegState(KillSrc));
379 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg));
382 .addReg(SrcReg, getKillRegState(KillSrc));
388 assert(AMDGPU::SReg_64RegClass.contains(SrcReg));
390 .addReg(SrcReg, getKillRegState(KillSrc))
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonExpandPredSpillCode.cpp | 243 // STriw_pred [R30], ofst, SrcReg;
249 int SrcReg = MI->getOperand(2).getReg();
250 assert(Hexagon::PredRegsRegClass.contains(SrcReg) &&
261 HEXAGON_RESERVED_REG_2).addReg(SrcReg);
270 HEXAGON_RESERVED_REG_2).addReg(SrcReg);
279 HEXAGON_RESERVED_REG_2).addReg(SrcReg);
|
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| r500_fragprog_emit.c | 415 use_temporary(code, inst->SrcReg[0].Index);
419 code->inst[ip].inst2 = R500_TEX_SRC_ADDR(inst->SrcReg[0].Index)
420 | (translate_strq_swizzle(inst->SrcReg[0].Swizzle) << 8)
429 use_temporary(code, inst->SrcReg[1].Index);
430 use_temporary(code, inst->SrcReg[2].Index);
434 R500_DX_ADDR(inst->SrcReg[1].Index) |
435 (translate_strq_swizzle(inst->SrcReg[1].Swizzle) << 8) |
436 R500_DY_ADDR(inst->SrcReg[2].Index) |
437 (translate_strq_swizzle(inst->SrcReg[2].Swizzle) << 24);
|
| r3xx_fragprog.c | 76 inst->SrcReg[i] = lmul_swizzle(RC_SWIZZLE_ZZZZ, inst->SrcReg[i]);
|
| radeon_program.h | 66 struct rc_src_register SrcReg[2];
78 struct rc_src_register SrcReg[3];
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIInstrInfo.h | 35 unsigned DestReg, unsigned SrcReg,
|
| R600InstrInfo.cpp | 51 unsigned DestReg, unsigned SrcReg,
55 && AMDGPU::R600_Reg128RegClass.contains(SrcReg)) {
60 .addReg(RI.getSubReg(SrcReg, SubRegIndex))
69 && !AMDGPU::R600_Reg128RegClass.contains(SrcReg));
72 .addReg(SrcReg, getKillRegState(KillSrc))
|
| /external/mesa3d/src/mesa/main/ |
| atifragshader.c | 684 curI->SrcReg[optype][0].Index = arg1;
685 curI->SrcReg[optype][0].argRep = arg1Rep;
686 curI->SrcReg[optype][0].argMod = arg1Mod;
690 curI->SrcReg[optype][1].Index = arg2;
691 curI->SrcReg[optype][1].argRep = arg2Rep;
692 curI->SrcReg[optype][1].argMod = arg2Mod;
696 curI->SrcReg[optype][2].Index = arg3;
697 curI->SrcReg[optype][2].argRep = arg3Rep;
698 curI->SrcReg[optype][2].argMod = arg3Mod;
|
| atifragshader.h | 55 struct atifragshader_src_register SrcReg[2][3];
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | 465 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>
478 unsigned SrcReg = MI.getOperand(0).getReg();
481 // an MFOCRF to save all of the CRBits and, if needed, kill the SrcReg.
483 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
487 if (SrcReg != PPC::CR0) {
494 .addImm(getEncodingValue(SrcReg) * 4)
553 MachineInstr &MI = *II; // ; SPILL_CRBIT <SrcReg>, <offset>
566 unsigned SrcReg = MI.getOperand(0).getReg();
569 getCRFromCRBit(SrcReg))
570 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()))
[all...] |
| PPCVSXSwapRemoval.cpp | 137 unsigned lookThruCopyLike(unsigned SrcReg, unsigned VecIdx);
152 // Insert a swap instruction from SrcReg to DstReg at the given
155 unsigned DstReg, unsigned SrcReg);
546 // the original SrcReg unless it is the target of a copy-like
552 unsigned PPCVSXSwapRemoval::lookThruCopyLike(unsigned SrcReg,
554 MachineInstr *MI = MRI->getVRegDef(SrcReg);
556 return SrcReg;
770 // FIXME: When inserting a swap, we should check whether SrcReg is
771 // defined by another swap: SrcReg = XXPERMDI Reg, Reg, 2; If so,
775 unsigned DstReg, unsigned SrcReg) {
[all...] |
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86AsmInstrumentation.cpp | 227 void InstrumentMOVSBase(unsigned DstReg, unsigned SrcReg, unsigned CntReg,
295 void X86AddressSanitizer::InstrumentMOVSBase(unsigned DstReg, unsigned SrcReg,
300 // and [SrcReg .. SrcReg + AccessSize * (CntReg - 1)].
306 RegCtx.AddBusyReg(SrcReg);
311 // Test (%SrcReg)
315 getPointerWidth(), 0, Disp, SrcReg, 0, AccessSize, SMLoc(), SMLoc()));
320 // Test -1(%SrcReg, %CntReg, AccessSize)
324 getPointerWidth(), 0, Disp, SrcReg, CntReg, AccessSize, SMLoc(),
748 InstrumentMOVSBase(X86::EDI /* DstReg */, X86::ESI /* SrcReg */,
[all...] |
| /external/llvm/lib/CodeGen/ |
| MachineCSE.cpp | 136 unsigned SrcReg = DefMI->getOperand(1).getReg();
137 if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
145 // RC = TRI->getMatchingSuperRegClass(MRI->getRegClass(SrcReg), RC,
147 // MO.substVirtReg(SrcReg, SrcSubReg, *TRI);
156 if (!MRI->constrainRegClass(SrcReg, RC))
160 // Propagate SrcReg of copies to MI.
161 MO.setReg(SrcReg);
162 MRI->clearKillFlags(SrcReg);
|
| TailDuplication.cpp | 263 unsigned SrcReg = LI->second[j].second;
264 SSAUpdate.AddAvailableValue(SrcBB, SrcReg);
372 unsigned SrcReg = MI.getOperand(i).getReg();
373 UsedByPhi->insert(SrcReg);
402 unsigned SrcReg = MI->getOperand(SrcOpIdx).getReg();
404 LocalVRMap.insert(std::make_pair(DefReg, SrcReg));
409 Copies.push_back(std::make_pair(NewDef, SrcReg));
516 unsigned SrcReg = LI->second[j].second;
518 II->getOperand(Idx).setReg(SrcReg);
522 MIB.addReg(SrcReg).addMBB(SrcBB)
[all...] |
| /external/llvm/lib/Target/Mips/ |
| Mips16InstrInfo.h | 48 unsigned DestReg, unsigned SrcReg,
53 unsigned SrcReg, bool isKill, int FrameIndex,
|
| MipsSEInstrInfo.h | 48 unsigned DestReg, unsigned SrcReg,
53 unsigned SrcReg, bool isKill, int FrameIndex,
|
| MipsOptimizePICCall.cpp | 134 unsigned SrcReg = I->getOperand(0).getReg();
135 unsigned DstReg = getRegTy(SrcReg, MF) == MVT::i32 ? Mips::T9 : Mips::T9_64;
137 .addReg(SrcReg);
|
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCCompound.cpp | 84 unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
115 SrcReg = MI.getOperand(1).getReg();
117 HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) &&
127 SrcReg = MI.getOperand(1).getReg();
129 HexagonMCInstrInfo::isIntRegForSubInst(SrcReg))
|
| /external/libvpx/libvpx/vpx_dsp/x86/ |
| vpx_subpixel_8t_intrin_ssse3.c | 63 __m128i addFilterReg64, filtersReg, srcReg, minReg;
89 srcReg = _mm_loadu_si128((const __m128i *)(src_ptr - 3));
92 srcRegFilt1= _mm_shuffle_epi8(srcReg, shuffle1);
93 srcRegFilt2= _mm_shuffle_epi8(srcReg, shuffle2);
132 __m128i firstFilters, secondFilters, thirdFilters, forthFilters, srcReg;
164 srcReg = _mm_loadu_si128((const __m128i *)(src_ptr - 3));
167 srcRegFilt1= _mm_shuffle_epi8(srcReg, filt1Reg);
168 srcRegFilt2= _mm_shuffle_epi8(srcReg, filt2Reg);
175 srcRegFilt3= _mm_shuffle_epi8(srcReg, filt3Reg);
176 srcRegFilt4= _mm_shuffle_epi8(srcReg, filt4Reg)
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_vs_emit.c | 40 /* Return the SrcReg index of the channels that can be immediate float operands
259 if (inst->SrcReg[arg].File != PROGRAM_STATE_VAR &&
260 inst->SrcReg[arg].File != PROGRAM_CONSTANT &&
261 inst->SrcReg[arg].File != PROGRAM_UNIFORM &&
262 inst->SrcReg[arg].File != PROGRAM_ENV_PARAM &&
263 inst->SrcReg[arg].File != PROGRAM_LOCAL_PARAM) {
267 if (inst->SrcReg[arg].RelAddr) {
272 if (c->constant_map[inst->SrcReg[arg].Index] == -1) {
273 c->constant_map[inst->SrcReg[arg].Index] = constant++;
1055 const struct prog_src_register *src = &inst->SrcReg[argIndex]
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.h | 197 unsigned &SrcReg, unsigned &DstReg,
334 unsigned DestReg, unsigned SrcReg,
338 unsigned SrcReg, bool isKill, int FrameIndex,
342 void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
502 /// in SrcReg and SrcReg2 if having two register operands, and the value it
505 bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
512 bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
|
| X86InstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcRegisterInfo.cpp | 186 unsigned SrcReg = MI.getOperand(2).getReg();
187 unsigned SrcEvenReg = getSubReg(SrcReg, SP::sub_even64);
188 unsigned SrcOddReg = getSubReg(SrcReg, SP::sub_odd64);
|
