| /external/llvm/lib/Target/AMDGPU/ |
| SIISelLowering.h | 62 bool isLegalFlatAddressingMode(const AddrMode &AM) const;
63 bool isLegalMUBUFAddressingMode(const AddrMode &AM) const;
70 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
|
| /external/llvm/lib/Target/ARM/ |
| Thumb2InstrInfo.cpp | 451 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
456 AddrMode = ARMII::AddrModeT2_i12; // FIXME. mode for thumb2?
526 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
532 if (AddrMode == ARMII::AddrModeT2_so) {
542 AddrMode = ARMII::AddrModeT2_i12;
547 if (AddrMode == ARMII::AddrModeT2_i8 || AddrMode == ARMII::AddrModeT2_i12) {
561 } else if (AddrMode == ARMII::AddrMode5) {
575 } else if (AddrMode == ARMII::AddrModeT2_i8s4)
[all...] |
| ARMInstrFormats.td | 90 class AddrMode<bits<5> val> {
93 def AddrModeNone : AddrMode<0>;
94 def AddrMode1 : AddrMode<1>;
95 def AddrMode2 : AddrMode<2>;
96 def AddrMode3 : AddrMode<3>;
97 def AddrMode4 : AddrMode<4>;
98 def AddrMode5 : AddrMode<5>;
99 def AddrMode6 : AddrMode<6>;
100 def AddrModeT1_1 : AddrMode<7>;
101 def AddrModeT1_2 : AddrMode<8>
[all...] |
| ARMInstrNEON.td | 666 class VLD1D<bits<4> op7_4, string Dt, Operand AddrMode>
668 (ins AddrMode:$Rn), IIC_VLD1,
674 class VLD1Q<bits<4> op7_4, string Dt, Operand AddrMode>
676 (ins AddrMode:$Rn), IIC_VLD1x2,
694 multiclass VLD1DWB<bits<4> op7_4, string Dt, Operand AddrMode> {
696 (ins AddrMode:$Rn), IIC_VLD1u,
704 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1u,
711 multiclass VLD1QWB<bits<4> op7_4, string Dt, Operand AddrMode> {
713 (ins AddrMode:$Rn), IIC_VLD1x2u,
721 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1x2u
[all...] |
| ARMBaseRegisterInfo.cpp | 424 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
428 switch (AddrMode) {
613 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
622 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
628 switch (AddrMode) {
|
| ThumbRegisterInfo.cpp | 364 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
375 if (AddrMode != ARMII::AddrModeT1_s)
590 // Use [reg, reg] addrmode. Replace the immediate operand w/ the frame
612 // Use [reg, reg] addrmode. Replace the immediate operand w/ the frame
|
| /prebuilts/go/darwin-x86/src/cmd/internal/rsc.io/arm/armasm/ |
| inst.go | 374 // An AddrMode is an ARM addressing mode.
375 type AddrMode uint8
378 _ AddrMode = iota
387 // The effective memory address is R or R+X depending on AddrMode.
392 Mode AddrMode
|
| decode.go | 450 mode := AddrMode(uint8(p<<1) | uint8(w^1))
476 mode := AddrMode(uint8(p<<1) | uint8(w^1))
497 mode := AddrMode(uint8(p<<1) | uint8(w^1))
|
| /prebuilts/go/linux-x86/src/cmd/internal/rsc.io/arm/armasm/ |
| inst.go | 374 // An AddrMode is an ARM addressing mode.
375 type AddrMode uint8
378 _ AddrMode = iota
387 // The effective memory address is R or R+X depending on AddrMode.
392 Mode AddrMode
|
| decode.go | 450 mode := AddrMode(uint8(p<<1) | uint8(w^1))
476 mode := AddrMode(uint8(p<<1) | uint8(w^1))
497 mode := AddrMode(uint8(p<<1) | uint8(w^1))
|
| /external/llvm/lib/CodeGen/ |
| CodeGenPrepare.cpp | [all...] |
| /prebuilts/go/darwin-x86/src/cmd/internal/rsc.io/x86/x86asm/ |
| decode.go | 262 addrMode = mode // address mode (width in bits)
388 addrMode = 16
391 addrMode = 32
468 if addrMode == 16 {
527 mem.Index = baseRegForBits(addrMode) + Reg(index)
532 mem.Base = baseRegForBits(addrMode) + Reg(base)
542 mem.Base = baseRegForBits(addrMode) + Reg(rm)
567 if addrMode == 32 {
669 switch addrMode {
896 if addrMode == 16
[all...] |
| /prebuilts/go/linux-x86/src/cmd/internal/rsc.io/x86/x86asm/ |
| decode.go | 262 addrMode = mode // address mode (width in bits)
388 addrMode = 16
391 addrMode = 32
468 if addrMode == 16 {
527 mem.Index = baseRegForBits(addrMode) + Reg(index)
532 mem.Base = baseRegForBits(addrMode) + Reg(base)
542 mem.Base = baseRegForBits(addrMode) + Reg(rm)
567 if addrMode == 32 {
669 switch addrMode {
896 if addrMode == 16
[all...] |
| /external/v8/src/arm64/ |
| simulator-arm64.h | 668 AddrMode addrmode);
669 void LoadStorePairHelper(Instruction* instr, AddrMode addrmode);
671 AddrMode addrmode);
674 AddrMode addrmode);
|
| assembler-arm64-inl.h | 466 MemOperand::MemOperand(Register base, int64_t offset, AddrMode addrmode)
467 : base_(base), regoffset_(NoReg), offset_(offset), addrmode_(addrmode),
500 MemOperand::MemOperand(Register base, const Operand& offset, AddrMode addrmode)
501 : base_(base), addrmode_(addrmode) {
509 DCHECK(addrmode == Offset);
523 DCHECK(addrmode == Offset);
[all...] |
| simulator-arm64.cc | [all...] |
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMBaseInfo.h | 235 enum AddrMode {
255 inline static const char *AddrModeToString(AddrMode addrmode) {
256 switch (addrmode) {
325 AddrModeMask = 0x1f, // The AddrMode enums are declared in ARMBaseInfo.h
|
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyISelLowering.h | 57 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
|
| /external/llvm/lib/Target/Hexagon/ |
| Hexagon.td | 147 let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"];
159 let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"];
169 let ColFields = ["addrMode"];
177 let ColFields = ["addrMode"];
|
| HexagonInstrInfoV60.td | 43 let addrMode = BaseImmOffset, accessSize = Vector64Access in
48 let isCodeGenOnly = 1, addrMode = BaseImmOffset, accessSize = Vector128Access in
105 let addrMode = BaseImmOffset, accessSize = Vector64Access in
144 let addrMode = BaseImmOffset, isNewValue = 1, opNewValue = 2, isNVStore = 1,
174 let addrMode = BaseImmOffset, isPredicated = 1 in
236 let addrMode = BaseImmOffset in
274 let addrMode = BaseImmOffset, isPredicated = 1, isNewValue = 1, opNewValue = 3,
322 let addrMode = PostInc, hasNewValue = 1 in
387 let addrMode = PostInc in
427 let addrMode = PostInc, isNVStore = 1 i
[all...] |
| HexagonISelLowering.h | 215 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.h | 316 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
324 int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty,
|
| /external/vixl/src/vixl/a64/ |
| simulator-a64.h | [all...] |
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonBaseInfo.h | 83 enum AddrMode {
|
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.h | 125 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
|
