| /toolchain/binutils/binutils-2.25/opcodes/ |
| cr16-opc.c | 162 /* opc4 c4 dispe9 */ \
164 /* opc4 c4 disps17 */ \
166 /* opc4 c4 disps25 */ \
294 #define CSTBIT_INST_B(NAME, OP, OPC1, OPC2, OPC3, OPC4) \
302 {NAME, 2, OPC4, 22, CSTBIT_INS, {{OP,4},{rpindex_disps14,0}}}, \
319 #define CSTBIT_INST_W(NAME, OP, OPC1, OPC2, OPC3, OPC4) \
327 {NAME, 2, OPC4, 22, CSTBIT_INS, {{OP,4},{rpindex_disps14,0}}}, \
350 #define LD_REG_INST(NAME, OPC1, OPC2, OPC3, OPC4, OPC5, OP_S, OP_D) \
357 /* opc4 reg disps4(RPbase) */ \
362 {NAME, 2, OPC4, 22, LD_STOR_INS, {{rpindex_disps14,0}, {OP_D,20}}},
[all...] |
| crx-opc.c | 109 /* opc4 c4 dispe9 */ \
111 /* opc4 c4 disps17 */ \
113 /* opc4 c4 disps32 */ \
355 /* opc4 r rbase dispu[bwd]4 */ \
358 /* opc4 r rbase disps16 */ \
361 /* opc4 r rbase disps32 */ \
384 /* opc4 r rbase dispu[bwd]4 */ \
387 /* opc4 r rbase disps16 */ \
390 /* opc4 r rbase disps32 */ \
545 /* opc12 c4 opc4 ui4 disps9 *
[all...] |
| crx-dis.c | 464 /* Case for opc4 r dispu rbase. */
|
| /external/llvm/lib/Target/X86/ |
| X86InstrControl.td | 85 multiclass ICBr<bits<8> opc1, bits<8> opc4, string asm, PatFrag Cond> {
89 def _2 : Ii16PCRel<opc4, RawFrm, (outs), (ins brtarget16:$dst), asm,
91 def _4 : Ii32PCRel<opc4, RawFrm, (outs), (ins brtarget32:$dst), asm,
|
| /external/valgrind/VEX/priv/ |
| guest_amd64_defs.h | 252 opc4 contains the 4th byte of opcode. Front-end should only
264 HWord opc4, HWord gstOffD,
|
| guest_amd64_helpers.c | 3807 HWord opc4 = (opc4_and_imm >> 8) & 0xFF; local
[all...] |
| /toolchain/binutils/binutils-2.25/cpu/ |
| m32c.cpu | [all...] |
