| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/aarch64/ |
| ldst-reg-unscaled-imm.s | 35 .macro op2 op, reg, simm
36 \op \reg\()7, [sp, #\simm]
41 .irp simm, -256, -171
42 op2 \op\suffix, \reg, \simm
45 .irp simm, 0, 2, 4, 8, 16, 85, 255
46 op2 \op\suffix, \reg, \simm
53 .irp simm, -256, -171
54 op2 \op, \reg, \simm
57 .irp simm, 0, 2, 4, 8, 16, 85, 255
58 op2 \op, \reg, \simm
[all...] |
| ldst-reg-imm-post-ind.s | 23 .macro op2 op, reg, simm
24 \op \reg\()7, [sp], #\simm
29 .irp simm, -256, -171, 0, 2, 4, 8, 16, 85, 255
30 op2 \op\suffix, \reg, \simm
37 .irp simm, -256, -171, 0, 2, 4, 8, 16, 85, 255
38 op2 \op, \reg, \simm
|
| ldst-reg-imm-pre-ind.s | 23 .macro op2 op, reg, simm
24 \op \reg\()7, [sp, #\simm]!
29 .irp simm, -256, -171, 0, 2, 4, 8, 16, 85, 255
30 op2 \op\suffix, \reg, \simm
37 .irp simm, -256, -171, 0, 2, 4, 8, 16, 85, 255
38 op2 \op, \reg, \simm
|
| ldst-reg-uns-imm.s | 37 .macro op2 op, reg, simm
38 \op \reg\()7, [sp, #\simm]
44 .irp simm, -256, -171
45 op2 \op\suffix, \reg, \simm
48 .irp simm, 0, 2, 4, 8, 16, 85, 255
49 op2 \op\suffix, \reg, \simm
57 .irp simm, -256, -171
58 op2 \op, \reg, \simm
61 .irp simm, 0, 2, 4, 8, 16, 85, 255
62 op2 \op, \reg, \simm
[all...] |
| /external/pcre/dist/sljit/ |
| sljitNativeARM_64.c | 413 static sljit_si load_immediate(struct sljit_compiler *compiler, sljit_si dst, sljit_sw simm)
415 sljit_uw imm = (sljit_uw)simm;
422 if (simm >= -0x10000 && simm < 0)
430 bitmask = logical_imm(simm, 16);
435 bitmask = logical_imm(simm, 32);
445 if (simm >= -0x100000000l && simm < 0) {
456 if ((simm & 0xffff) == 0)
458 if ((simm & 0xffff) == 0xffff
[all...] |
| /external/llvm/lib/Target/AMDGPU/InstPrinter/ |
| AMDGPUInstPrinter.cpp | 233 int32_t SImm = static_cast<int32_t>(Imm);
234 if (SImm >= -16 && SImm <= 64) {
235 O << SImm;
262 int64_t SImm = static_cast<int64_t>(Imm);
263 if (SImm >= -16 && SImm <= 64) {
264 O << SImm;
|
| /external/llvm/lib/Target/ARM/ |
| ARMInstrNEON.td | [all...] |
| ARMInstrFormats.td | [all...] |
| /toolchain/binutils/binutils-2.25/cpu/ |
| frv.cpu | [all...] |
| or1korbis.cpu | 883 (define-pmacro (alu-insn-simm mnemonic)
911 (alu-insn-simm xor)
913 (define-pmacro (alu-carry-insn-simm mnemonic)
934 (alu-carry-insn-simm add)
[all...] |
| /external/llvm/lib/Target/SystemZ/InstPrinter/ |
| SystemZInstPrinter.cpp | 73 assert(isInt<N>(Value) && "Invalid simm argument");
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrAltivec.td | [all...] |
| /system/core/libpixelflinger/codeflinger/ |
| Arm64Assembler.cpp | 1021 uint32_t Rn, int32_t simm)
1024 LOG_INSTR("STR W%d, [SP, #%d]!\n", Rt, simm);
1026 LOG_INSTR("STR W%d, [X%d, #%d]!\n", Rt, Rn, simm);
1028 uint32_t imm9 = (unsigned)(simm) & 0x01FF;
1033 uint32_t Rn, int32_t simm)
1036 LOG_INSTR("LDR W%d, [SP], #%d\n",Rt,simm);
1038 LOG_INSTR("LDR W%d, [X%d], #%d\n",Rt, Rn, simm);
1040 uint32_t imm9 = (unsigned)(simm) & 0x01FF;
[all...] |
| Arm64Assembler.h | 201 uint32_t A64_STR_IMM_PreIndex(uint32_t Rt, uint32_t Rn, int32_t simm);
202 uint32_t A64_LDR_IMM_PostIndex(uint32_t Rt,uint32_t Rn, int32_t simm);
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCCodeEmitter.cpp | 566 int32_t SImm = MO1.getImm();
570 if (SImm == INT32_MIN) {
571 SImm = 0;
576 if (SImm < 0) {
577 SImm = -SImm;
581 Imm = SImm;
[all...] |
| /external/valgrind/VEX/priv/ |
| host_arm64_defs.h | 644 Int simm; /* needs to be 0 % 16 and in the range -4095 member in struct:__anon25559::__anon25560::__anon25578
905 extern ARM64Instr* ARM64Instr_AddToSP ( Int simm );
[all...] |
| host_arm_isel.c | 777 Int simm = (Int)e->Iex.Binop.arg2->Iex.Const.con->Ico.U32; local
778 if (simm >= -4095 && simm <= 4095) {
781 simm = -simm;
783 return ARMAMode1_RI(reg, simm);
843 Int simm = (Int)e->Iex.Binop.arg2->Iex.Const.con->Ico.U32; local
844 if (simm >= -255 && simm <= 255) {
847 simm = -simm
895 Int simm = (Int)e->Iex.Binop.arg2->Iex.Const.con->Ico.U32; local
[all...] |
| guest_arm64_toIR.c | 2466 ULong simm = sx_to_64(uimm, 21); local
[all...] |
| host_arm64_defs.c | 1524 Int simm = i->ARM64in.AddToSP.simm; local
[all...] |
| host_arm64_isel.c | 873 Long simm = (Long)e->Iex.Binop.arg2->Iex.Const.con->Ico.U64; local
874 if (simm >= -255 && simm <= 255) {
876 simm >= -256 && simm <= 255
877 we will need to negate simm in the case where the op is Sub64.
881 if (e->Iex.Binop.op == Iop_Sub64) simm = -simm;
882 return ARM64AMode_RI9(reg, (Int)simm);
[all...] |
| /prebuilts/go/darwin-x86/pkg/bootstrap/pkg/darwin_amd64/bootstrap/internal/obj/ |
| ppc64.a | 471 func @"".AOP_IRR (@"".op·2 uint32, @"".d·3 uint32, @"".a·4 uint32, @"".simm·5 uint32) (? uint32) { return @"".op·2 | @"".d·3 & 0x1f << 0x15 | @"".a·4 & 0x1f << 0x10 | @"".simm·5 & 0xffff }
[all...] |
| /prebuilts/go/darwin-x86/pkg/darwin_amd64/cmd/internal/obj/ |
| ppc64.a | 471 func @"".AOP_IRR (@"".op·2 uint32, @"".d·3 uint32, @"".a·4 uint32, @"".simm·5 uint32) (? uint32) { return @"".op·2 | @"".d·3 & 0x1f << 0x15 | @"".a·4 & 0x1f << 0x10 | @"".simm·5 & 0xffff }
[all...] |
| /prebuilts/go/linux-x86/pkg/bootstrap/pkg/linux_amd64/bootstrap/internal/obj/ |
| ppc64.a | 471 func @"".AOP_IRR (@"".op·2 uint32, @"".d·3 uint32, @"".a·4 uint32, @"".simm·5 uint32) (? uint32) { return @"".op·2 | @"".d·3 & 0x1f << 0x15 | @"".a·4 & 0x1f << 0x10 | @"".simm·5 & 0xffff }
[all...] |
| /prebuilts/go/linux-x86/pkg/linux_amd64/cmd/internal/obj/ |
| ppc64.a | 471 func @"".AOP_IRR (@"".op·2 uint32, @"".d·3 uint32, @"".a·4 uint32, @"".simm·5 uint32) (? uint32) { return @"".op·2 | @"".d·3 & 0x1f << 0x15 | @"".a·4 & 0x1f << 0x10 | @"".simm·5 & 0xffff }
[all...] |
| /toolchain/binutils/binutils-2.25/opcodes/ |
| aarch64-asm.c | 533 /* Encode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>, #<simm>]!. */
544 /* simm (imm9 or imm7) */
[all...] |
