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      1 //===-- InterferenceCache.cpp - Caching per-block interference ---------*--===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // InterferenceCache remembers per-block interference in LiveIntervalUnions.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #include "InterferenceCache.h"
     15 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
     16 #include "llvm/Support/ErrorHandling.h"
     17 #include "llvm/Target/TargetRegisterInfo.h"
     18 
     19 using namespace llvm;
     20 
     21 #define DEBUG_TYPE "regalloc"
     22 
     23 // Static member used for null interference cursors.
     24 const InterferenceCache::BlockInterference
     25     InterferenceCache::Cursor::NoInterference;
     26 
     27 // Initializes PhysRegEntries (instead of a SmallVector, PhysRegEntries is a
     28 // buffer of size NumPhysRegs to speed up alloc/clear for targets with large
     29 // reg files). Calloced memory is used for good form, and quites tools like
     30 // Valgrind too, but zero initialized memory is not required by the algorithm:
     31 // this is because PhysRegEntries works like a SparseSet and its entries are
     32 // only valid when there is a corresponding CacheEntries assignment. There is
     33 // also support for when pass managers are reused for targets with different
     34 // numbers of PhysRegs: in this case PhysRegEntries is freed and reinitialized.
     35 void InterferenceCache::reinitPhysRegEntries() {
     36   if (PhysRegEntriesCount == TRI->getNumRegs()) return;
     37   free(PhysRegEntries);
     38   PhysRegEntriesCount = TRI->getNumRegs();
     39   PhysRegEntries = (unsigned char*)
     40     calloc(PhysRegEntriesCount, sizeof(unsigned char));
     41 }
     42 
     43 void InterferenceCache::init(MachineFunction *mf,
     44                              LiveIntervalUnion *liuarray,
     45                              SlotIndexes *indexes,
     46                              LiveIntervals *lis,
     47                              const TargetRegisterInfo *tri) {
     48   MF = mf;
     49   LIUArray = liuarray;
     50   TRI = tri;
     51   reinitPhysRegEntries();
     52   for (unsigned i = 0; i != CacheEntries; ++i)
     53     Entries[i].clear(mf, indexes, lis);
     54 }
     55 
     56 InterferenceCache::Entry *InterferenceCache::get(unsigned PhysReg) {
     57   unsigned E = PhysRegEntries[PhysReg];
     58   if (E < CacheEntries && Entries[E].getPhysReg() == PhysReg) {
     59     if (!Entries[E].valid(LIUArray, TRI))
     60       Entries[E].revalidate(LIUArray, TRI);
     61     return &Entries[E];
     62   }
     63   // No valid entry exists, pick the next round-robin entry.
     64   E = RoundRobin;
     65   if (++RoundRobin == CacheEntries)
     66     RoundRobin = 0;
     67   for (unsigned i = 0; i != CacheEntries; ++i) {
     68     // Skip entries that are in use.
     69     if (Entries[E].hasRefs()) {
     70       if (++E == CacheEntries)
     71         E = 0;
     72       continue;
     73     }
     74     Entries[E].reset(PhysReg, LIUArray, TRI, MF);
     75     PhysRegEntries[PhysReg] = E;
     76     return &Entries[E];
     77   }
     78   llvm_unreachable("Ran out of interference cache entries.");
     79 }
     80 
     81 /// revalidate - LIU contents have changed, update tags.
     82 void InterferenceCache::Entry::revalidate(LiveIntervalUnion *LIUArray,
     83                                           const TargetRegisterInfo *TRI) {
     84   // Invalidate all block entries.
     85   ++Tag;
     86   // Invalidate all iterators.
     87   PrevPos = SlotIndex();
     88   unsigned i = 0;
     89   for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units, ++i)
     90     RegUnits[i].VirtTag = LIUArray[*Units].getTag();
     91 }
     92 
     93 void InterferenceCache::Entry::reset(unsigned physReg,
     94                                      LiveIntervalUnion *LIUArray,
     95                                      const TargetRegisterInfo *TRI,
     96                                      const MachineFunction *MF) {
     97   assert(!hasRefs() && "Cannot reset cache entry with references");
     98   // LIU's changed, invalidate cache.
     99   ++Tag;
    100   PhysReg = physReg;
    101   Blocks.resize(MF->getNumBlockIDs());
    102 
    103   // Reset iterators.
    104   PrevPos = SlotIndex();
    105   RegUnits.clear();
    106   for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
    107     RegUnits.push_back(LIUArray[*Units]);
    108     RegUnits.back().Fixed = &LIS->getRegUnit(*Units);
    109   }
    110 }
    111 
    112 bool InterferenceCache::Entry::valid(LiveIntervalUnion *LIUArray,
    113                                      const TargetRegisterInfo *TRI) {
    114   unsigned i = 0, e = RegUnits.size();
    115   for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units, ++i) {
    116     if (i == e)
    117       return false;
    118     if (LIUArray[*Units].changedSince(RegUnits[i].VirtTag))
    119       return false;
    120   }
    121   return i == e;
    122 }
    123 
    124 void InterferenceCache::Entry::update(unsigned MBBNum) {
    125   SlotIndex Start, Stop;
    126   std::tie(Start, Stop) = Indexes->getMBBRange(MBBNum);
    127 
    128   // Use advanceTo only when possible.
    129   if (PrevPos != Start) {
    130     if (!PrevPos.isValid() || Start < PrevPos) {
    131       for (unsigned i = 0, e = RegUnits.size(); i != e; ++i) {
    132         RegUnitInfo &RUI = RegUnits[i];
    133         RUI.VirtI.find(Start);
    134         RUI.FixedI = RUI.Fixed->find(Start);
    135       }
    136     } else {
    137       for (unsigned i = 0, e = RegUnits.size(); i != e; ++i) {
    138         RegUnitInfo &RUI = RegUnits[i];
    139         RUI.VirtI.advanceTo(Start);
    140         if (RUI.FixedI != RUI.Fixed->end())
    141           RUI.FixedI = RUI.Fixed->advanceTo(RUI.FixedI, Start);
    142       }
    143     }
    144     PrevPos = Start;
    145   }
    146 
    147   MachineFunction::const_iterator MFI =
    148       MF->getBlockNumbered(MBBNum)->getIterator();
    149   BlockInterference *BI = &Blocks[MBBNum];
    150   ArrayRef<SlotIndex> RegMaskSlots;
    151   ArrayRef<const uint32_t*> RegMaskBits;
    152   for (;;) {
    153     BI->Tag = Tag;
    154     BI->First = BI->Last = SlotIndex();
    155 
    156     // Check for first interference from virtregs.
    157     for (unsigned i = 0, e = RegUnits.size(); i != e; ++i) {
    158       LiveIntervalUnion::SegmentIter &I = RegUnits[i].VirtI;
    159       if (!I.valid())
    160         continue;
    161       SlotIndex StartI = I.start();
    162       if (StartI >= Stop)
    163         continue;
    164       if (!BI->First.isValid() || StartI < BI->First)
    165         BI->First = StartI;
    166     }
    167 
    168     // Same thing for fixed interference.
    169     for (unsigned i = 0, e = RegUnits.size(); i != e; ++i) {
    170       LiveInterval::const_iterator I = RegUnits[i].FixedI;
    171       LiveInterval::const_iterator E = RegUnits[i].Fixed->end();
    172       if (I == E)
    173         continue;
    174       SlotIndex StartI = I->start;
    175       if (StartI >= Stop)
    176         continue;
    177       if (!BI->First.isValid() || StartI < BI->First)
    178         BI->First = StartI;
    179     }
    180 
    181     // Also check for register mask interference.
    182     RegMaskSlots = LIS->getRegMaskSlotsInBlock(MBBNum);
    183     RegMaskBits = LIS->getRegMaskBitsInBlock(MBBNum);
    184     SlotIndex Limit = BI->First.isValid() ? BI->First : Stop;
    185     for (unsigned i = 0, e = RegMaskSlots.size();
    186          i != e && RegMaskSlots[i] < Limit; ++i)
    187       if (MachineOperand::clobbersPhysReg(RegMaskBits[i], PhysReg)) {
    188         // Register mask i clobbers PhysReg before the LIU interference.
    189         BI->First = RegMaskSlots[i];
    190         break;
    191       }
    192 
    193     PrevPos = Stop;
    194     if (BI->First.isValid())
    195       break;
    196 
    197     // No interference in this block? Go ahead and precompute the next block.
    198     if (++MFI == MF->end())
    199       return;
    200     MBBNum = MFI->getNumber();
    201     BI = &Blocks[MBBNum];
    202     if (BI->Tag == Tag)
    203       return;
    204     std::tie(Start, Stop) = Indexes->getMBBRange(MBBNum);
    205   }
    206 
    207   // Check for last interference in block.
    208   for (unsigned i = 0, e = RegUnits.size(); i != e; ++i) {
    209     LiveIntervalUnion::SegmentIter &I = RegUnits[i].VirtI;
    210     if (!I.valid() || I.start() >= Stop)
    211       continue;
    212     I.advanceTo(Stop);
    213     bool Backup = !I.valid() || I.start() >= Stop;
    214     if (Backup)
    215       --I;
    216     SlotIndex StopI = I.stop();
    217     if (!BI->Last.isValid() || StopI > BI->Last)
    218       BI->Last = StopI;
    219     if (Backup)
    220       ++I;
    221   }
    222 
    223   // Fixed interference.
    224   for (unsigned i = 0, e = RegUnits.size(); i != e; ++i) {
    225     LiveInterval::iterator &I = RegUnits[i].FixedI;
    226     LiveRange *LR = RegUnits[i].Fixed;
    227     if (I == LR->end() || I->start >= Stop)
    228       continue;
    229     I = LR->advanceTo(I, Stop);
    230     bool Backup = I == LR->end() || I->start >= Stop;
    231     if (Backup)
    232       --I;
    233     SlotIndex StopI = I->end;
    234     if (!BI->Last.isValid() || StopI > BI->Last)
    235       BI->Last = StopI;
    236     if (Backup)
    237       ++I;
    238   }
    239 
    240   // Also check for register mask interference.
    241   SlotIndex Limit = BI->Last.isValid() ? BI->Last : Start;
    242   for (unsigned i = RegMaskSlots.size();
    243        i && RegMaskSlots[i-1].getDeadSlot() > Limit; --i)
    244     if (MachineOperand::clobbersPhysReg(RegMaskBits[i-1], PhysReg)) {
    245       // Register mask i-1 clobbers PhysReg after the LIU interference.
    246       // Model the regmask clobber as a dead def.
    247       BI->Last = RegMaskSlots[i-1].getDeadSlot();
    248       break;
    249     }
    250 }
    251