1 //===----------------------- AMDGPUFrameLowering.cpp ----------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //==-----------------------------------------------------------------------===// 9 // 10 // Interface to describe a layout of a stack frame on a AMDIL target machine 11 // 12 //===----------------------------------------------------------------------===// 13 #include "AMDGPUFrameLowering.h" 14 #include "AMDGPURegisterInfo.h" 15 #include "R600MachineFunctionInfo.h" 16 #include "llvm/CodeGen/MachineFrameInfo.h" 17 #include "llvm/CodeGen/MachineRegisterInfo.h" 18 #include "llvm/IR/Instructions.h" 19 20 using namespace llvm; 21 AMDGPUFrameLowering::AMDGPUFrameLowering(StackDirection D, unsigned StackAl, 22 int LAO, unsigned TransAl) 23 : TargetFrameLowering(D, StackAl, LAO, TransAl) { } 24 25 AMDGPUFrameLowering::~AMDGPUFrameLowering() { } 26 27 unsigned AMDGPUFrameLowering::getStackWidth(const MachineFunction &MF) const { 28 29 // XXX: Hardcoding to 1 for now. 30 // 31 // I think the StackWidth should stored as metadata associated with the 32 // MachineFunction. This metadata can either be added by a frontend, or 33 // calculated by a R600 specific LLVM IR pass. 34 // 35 // The StackWidth determines how stack objects are laid out in memory. 36 // For a vector stack variable, like: int4 stack[2], the data will be stored 37 // in the following ways depending on the StackWidth. 38 // 39 // StackWidth = 1: 40 // 41 // T0.X = stack[0].x 42 // T1.X = stack[0].y 43 // T2.X = stack[0].z 44 // T3.X = stack[0].w 45 // T4.X = stack[1].x 46 // T5.X = stack[1].y 47 // T6.X = stack[1].z 48 // T7.X = stack[1].w 49 // 50 // StackWidth = 2: 51 // 52 // T0.X = stack[0].x 53 // T0.Y = stack[0].y 54 // T1.X = stack[0].z 55 // T1.Y = stack[0].w 56 // T2.X = stack[1].x 57 // T2.Y = stack[1].y 58 // T3.X = stack[1].z 59 // T3.Y = stack[1].w 60 // 61 // StackWidth = 4: 62 // T0.X = stack[0].x 63 // T0.Y = stack[0].y 64 // T0.Z = stack[0].z 65 // T0.W = stack[0].w 66 // T1.X = stack[1].x 67 // T1.Y = stack[1].y 68 // T1.Z = stack[1].z 69 // T1.W = stack[1].w 70 return 1; 71 } 72 73 /// \returns The number of registers allocated for \p FI. 74 int AMDGPUFrameLowering::getFrameIndexReference(const MachineFunction &MF, 75 int FI, 76 unsigned &FrameReg) const { 77 const MachineFrameInfo *MFI = MF.getFrameInfo(); 78 const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo(); 79 80 // Fill in FrameReg output argument. 81 FrameReg = RI->getFrameRegister(MF); 82 83 // Start the offset at 2 so we don't overwrite work group information. 84 // XXX: We should only do this when the shader actually uses this 85 // information. 86 unsigned OffsetBytes = 2 * (getStackWidth(MF) * 4); 87 int UpperBound = FI == -1 ? MFI->getNumObjects() : FI; 88 89 for (int i = MFI->getObjectIndexBegin(); i < UpperBound; ++i) { 90 OffsetBytes = RoundUpToAlignment(OffsetBytes, MFI->getObjectAlignment(i)); 91 OffsetBytes += MFI->getObjectSize(i); 92 // Each register holds 4 bytes, so we must always align the offset to at 93 // least 4 bytes, so that 2 frame objects won't share the same register. 94 OffsetBytes = RoundUpToAlignment(OffsetBytes, 4); 95 } 96 97 if (FI != -1) 98 OffsetBytes = RoundUpToAlignment(OffsetBytes, MFI->getObjectAlignment(FI)); 99 100 return OffsetBytes / (getStackWidth(MF) * 4); 101 } 102 103 const TargetFrameLowering::SpillSlot * 104 AMDGPUFrameLowering::getCalleeSavedSpillSlots(unsigned &NumEntries) const { 105 NumEntries = 0; 106 return nullptr; 107 } 108 void AMDGPUFrameLowering::emitPrologue(MachineFunction &MF, 109 MachineBasicBlock &MBB) const {} 110 void 111 AMDGPUFrameLowering::emitEpilogue(MachineFunction &MF, 112 MachineBasicBlock &MBB) const { 113 } 114 115 bool 116 AMDGPUFrameLowering::hasFP(const MachineFunction &MF) const { 117 return false; 118 } 119
