1 //===-- ARMTargetTransformInfo.h - ARM specific TTI -------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 /// \file 10 /// This file a TargetTransformInfo::Concept conforming object specific to the 11 /// ARM target machine. It uses the target's detailed information to 12 /// provide more precise answers to certain TTI queries, while letting the 13 /// target independent and default TTI implementations handle the rest. 14 /// 15 //===----------------------------------------------------------------------===// 16 17 #ifndef LLVM_LIB_TARGET_ARM_ARMTARGETTRANSFORMINFO_H 18 #define LLVM_LIB_TARGET_ARM_ARMTARGETTRANSFORMINFO_H 19 20 #include "ARM.h" 21 #include "ARMTargetMachine.h" 22 #include "llvm/Analysis/TargetTransformInfo.h" 23 #include "llvm/CodeGen/BasicTTIImpl.h" 24 #include "llvm/Target/TargetLowering.h" 25 26 namespace llvm { 27 28 class ARMTTIImpl : public BasicTTIImplBase<ARMTTIImpl> { 29 typedef BasicTTIImplBase<ARMTTIImpl> BaseT; 30 typedef TargetTransformInfo TTI; 31 friend BaseT; 32 33 const ARMSubtarget *ST; 34 const ARMTargetLowering *TLI; 35 36 /// Estimate the overhead of scalarizing an instruction. Insert and Extract 37 /// are set if the result needs to be inserted and/or extracted from vectors. 38 unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract); 39 40 const ARMSubtarget *getST() const { return ST; } 41 const ARMTargetLowering *getTLI() const { return TLI; } 42 43 public: 44 explicit ARMTTIImpl(const ARMBaseTargetMachine *TM, const Function &F) 45 : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)), 46 TLI(ST->getTargetLowering()) {} 47 48 // Provide value semantics. MSVC requires that we spell all of these out. 49 ARMTTIImpl(const ARMTTIImpl &Arg) 50 : BaseT(static_cast<const BaseT &>(Arg)), ST(Arg.ST), TLI(Arg.TLI) {} 51 ARMTTIImpl(ARMTTIImpl &&Arg) 52 : BaseT(std::move(static_cast<BaseT &>(Arg))), ST(std::move(Arg.ST)), 53 TLI(std::move(Arg.TLI)) {} 54 55 bool enableInterleavedAccessVectorization() { return true; } 56 57 /// \name Scalar TTI Implementations 58 /// @{ 59 60 using BaseT::getIntImmCost; 61 int getIntImmCost(const APInt &Imm, Type *Ty); 62 63 /// @} 64 65 /// \name Vector TTI Implementations 66 /// @{ 67 68 unsigned getNumberOfRegisters(bool Vector) { 69 if (Vector) { 70 if (ST->hasNEON()) 71 return 16; 72 return 0; 73 } 74 75 if (ST->isThumb1Only()) 76 return 8; 77 return 13; 78 } 79 80 unsigned getRegisterBitWidth(bool Vector) { 81 if (Vector) { 82 if (ST->hasNEON()) 83 return 128; 84 return 0; 85 } 86 87 return 32; 88 } 89 90 unsigned getMaxInterleaveFactor(unsigned VF) { 91 // These are out of order CPUs: 92 if (ST->isCortexA15() || ST->isSwift()) 93 return 2; 94 return 1; 95 } 96 97 int getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, Type *SubTp); 98 99 int getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src); 100 101 int getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy); 102 103 int getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index); 104 105 int getAddressComputationCost(Type *Val, bool IsComplex); 106 107 int getFPOpCost(Type *Ty); 108 109 int getArithmeticInstrCost( 110 unsigned Opcode, Type *Ty, 111 TTI::OperandValueKind Op1Info = TTI::OK_AnyValue, 112 TTI::OperandValueKind Op2Info = TTI::OK_AnyValue, 113 TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None, 114 TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None); 115 116 int getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, 117 unsigned AddressSpace); 118 119 int getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, 120 ArrayRef<unsigned> Indices, unsigned Alignment, 121 unsigned AddressSpace); 122 /// @} 123 }; 124 125 } // end namespace llvm 126 127 #endif 128