| /external/llvm/lib/Target/MSP430/InstPrinter/ |
| MSP430InstPrinter.cpp | 65 const MCOperand &Disp = MI->getOperand(OpNo+1);
78 if (Disp.isExpr())
79 Disp.getExpr()->print(O, &MAI);
81 assert(Disp.isImm() && "Expected immediate in displacement field");
82 O << Disp.getImm();
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430AsmPrinter.cpp | 108 const MachineOperand &Disp = MI->getOperand(OpNum+1);
113 if (Disp.isImm() && !Base.getReg())
|
| MSP430ISelDAGToDAG.cpp | 48 int16_t Disp;
57 : BaseType(RegBase), Disp(0), GV(nullptr), CP(nullptr),
73 errs() << " Disp " << Disp << '\n';
119 bool SelectAddr(SDValue Addr, SDValue &Base, SDValue &Disp);
145 AM.Disp += G->getOffset();
150 AM.Disp += CP->getOffset();
187 AM.Disp += Val;
230 AM.Disp += Offset;
245 SDValue &Base, SDValue &Disp) {
[all...] |
| /external/llvm/lib/Target/SystemZ/InstPrinter/ |
| SystemZInstPrinter.cpp | 24 void SystemZInstPrinter::printAddress(unsigned Base, int64_t Disp,
26 O << Disp;
198 uint64_t Disp = MI->getOperand(OpNum + 1).getImm();
200 O << Disp << '(' << Length;
|
| /external/llvm/lib/Target/X86/ |
| X86InstrBuilder.h | 35 /// with BP or SP and Disp being offsetted accordingly. The displacement may
50 int Disp;
55 : BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(nullptr),
77 MO.push_back(MachineOperand::CreateGA(GV, Disp, GVOpFlags));
79 MO.push_back(MachineOperand::CreateImm(Disp));
136 MIB.addGlobalAddress(AM.GV, AM.Disp, AM.GVOpFlags);
138 MIB.addImm(AM.Disp);
|
| X86ISelDAGToDAG.cpp | 63 int32_t Disp;
75 : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0),
118 dbgs() << " Disp " << Disp << '\n'
212 SDValue &Scale, SDValue &Index, SDValue &Disp,
215 SDValue &Scale, SDValue &Index, SDValue &Disp,
219 SDValue &Scale, SDValue &Index, SDValue &Disp,
222 SDValue &Scale, SDValue &Index, SDValue &Disp,
225 SDValue &Scale, SDValue &Index, SDValue &Disp,
229 SDValue &Index, SDValue &Disp,
[all...] |
| X86FastISel.cpp | 663 // Now construct the final address. Note that the Disp, Scale,
749 uint64_t Disp = (int32_t)AM.Disp + (uint64_t)CI->getSExtValue();
751 if (isInt<32>(Disp)) {
752 AM.Disp = (uint32_t)Disp;
763 uint64_t Disp = (int32_t)AM.Disp;
774 Disp += SL->getElementOffset(cast<ConstantInt>(Op)->getZExtValue());
784 Disp += CI->getSExtValue() * S
[all...] |
| /external/llvm/lib/Target/SystemZ/MCTargetDesc/ |
| SystemZMCCodeEmitter.cpp | 152 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI);
153 assert(isUInt<4>(Base) && isUInt<12>(Disp));
154 return (Base << 12) | Disp;
162 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI);
163 assert(isUInt<4>(Base) && isInt<20>(Disp));
164 return (Base << 20) | ((Disp & 0xfff) << 8) | ((Disp & 0xff000) >> 12);
172 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI);
174 assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<4>(Index));
175 return (Index << 16) | (Base << 12) | Disp;
[all...] |
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86AsmInstrumentation.cpp | 313 const MCExpr *Disp = MCConstantExpr::create(0, Ctx);
315 getPointerWidth(), 0, Disp, SrcReg, 0, AccessSize, SMLoc(), SMLoc()));
322 const MCExpr *Disp = MCConstantExpr::create(-1, Ctx);
324 getPointerWidth(), 0, Disp, SrcReg, CntReg, AccessSize, SMLoc(),
332 const MCExpr *Disp = MCConstantExpr::create(0, Ctx);
334 getPointerWidth(), 0, Disp, DstReg, 0, AccessSize, SMLoc(), SMLoc()));
340 const MCExpr *Disp = MCConstantExpr::create(-1, Ctx);
342 getPointerWidth(), 0, Disp, DstReg, CntReg, AccessSize, SMLoc(),
458 const MCConstantExpr *Disp =
461 X86Operand::CreateMem(getPointerWidth(), 0, Disp, Reg, 0, 1, SMLoc()
[all...] |
| X86Operand.h | 54 const MCExpr *Disp;
109 return Mem.Disp;
496 CreateMem(unsigned ModeSize, const MCExpr *Disp, SMLoc StartLoc, SMLoc EndLoc,
501 Res->Mem.Disp = Disp;
515 CreateMem(unsigned ModeSize, unsigned SegReg, const MCExpr *Disp,
528 Res->Mem.Disp = Disp;
|
| X86AsmParser.cpp | 694 bool ParseIntelDotOperator(const MCExpr *Disp, const MCExpr *&NewDisp);
713 CreateMemForInlineAsm(unsigned SegReg, const MCExpr *Disp, unsigned BaseReg,
[all...] |
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCCodeEmitter.cpp | 62 const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp);
65 Disp.isImm() && Disp.getImm() < 0x10000)
122 void EmitImmediate(const MCOperand &Disp, SMLoc Loc,
368 const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp);
396 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(FixupKind),
440 if (Disp.isImm() && isDisp8(Disp.getImm())) {
441 if (Disp.getImm() == 0 && BaseRegNo != N86::EBP) {
448 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups)
[all...] |
| /toolchain/binutils/binutils-2.25/include/opcode/ |
| tic30.h | 198 #define Disp 0x0080
261 { "b" ,1,0x68000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
262 { "bu" ,1,0x68000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
263 { "blo" ,1,0x68010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
264 { "bls" ,1,0x68020000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
265 { "bhi" ,1,0x68030000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
266 { "bhs" ,1,0x68040000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
267 { "beq" ,1,0x68050000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
268 { "bne" ,1,0x68060000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
269 { "blt" ,1,0x68070000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelDAGToDAG.cpp | 57 // Base + Disp + Index + (IncludesDynAlloc ? ADJDYNALLOC : 0)
59 int64_t Disp;
64 : Form(form), DR(dr), Base(), Disp(0), Index(),
90 errs() << " Disp " << Disp;
157 SDValue &Base, SDValue &Disp) const;
159 SDValue &Base, SDValue &Disp, SDValue &Index) const;
163 // Base and Disp respectively.
165 SDValue &Base, SDValue &Disp) const;
169 // base and displacement in Base and Disp respectively
[all...] |
| /external/llvm/lib/Transforms/IPO/ |
| LowerBitSets.cpp | 682 Constant *Disp = ConstantExpr::getSub(DestInt, SrcInt);
685 Constant *OffsetedDisp = ConstantExpr::getSub(Disp, DispOffset);
[all...] |
| /external/llvm/lib/Target/SystemZ/AsmParser/ |
| SystemZAsmParser.cpp | 91 // Base + Disp + Index, where Base and Index are LLVM registers or 0.
100 const MCExpr *Disp;
166 const MCExpr *Disp, unsigned Index, const MCExpr *Length,
173 Op->Mem.Disp = Disp;
245 return isMem(MemKind, RegKind) && inRange(Mem.Disp, 0, 0xfff);
248 return isMem(MemKind, RegKind) && inRange(Mem.Disp, -524288, 524287);
257 addExpr(Inst, Mem.Disp);
285 addExpr(Inst, Mem.Disp);
291 addExpr(Inst, Mem.Disp);
[all...] |
