| /external/llvm/lib/Transforms/IPO/ |
| IPConstantPropagation.cpp | 250 Instruction *Ins = cast<Instruction>(*I);
257 if (ExtractValueInst *EV = dyn_cast<ExtractValueInst>(Ins))
270 Ins->replaceAllUsesWith(New);
271 Ins->eraseFromParent();
|
| PartialInlining.cpp | 94 Instruction *Ins = &newReturnBlock->front();
99 PHINode *retPhi = PHINode::Create(OldPhi->getType(), 2, "", Ins);
101 Ins = newReturnBlock->getFirstNonPHI();
|
| LowerBitSets.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64RegisterInfo.cpp | 320 MachineBasicBlock::iterator Ins = MBB->begin();
322 if (Ins != MBB->end())
323 DL = Ins->getDebugLoc();
332 BuildMI(*MBB, Ins, DL, MCID, BaseReg)
|
| /external/llvm/include/llvm/CodeGen/ |
| FastISel.h | 84 SmallVector<ISD::InputArg, 4> Ins;
186 Ins.clear();
|
| /external/llvm/lib/Target/BPF/ |
| BPFISelLowering.cpp | 190 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
206 CCInfo.AnalyzeFormalArguments(Ins, CC_BPF64);
260 auto &Ins = CLI.Ins;
382 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, CLI.DL, DAG,
437 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
445 if (Ins.size() >= 2) {
451 CCInfo.AnalyzeCallResult(Ins, RetCC_BPF64);
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | [all...] |
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyISelLowering.cpp | 342 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
343 if (Ins.size() > 1)
427 for (const auto &In : Ins) {
444 DAG.getNode(Ins.empty() ? WebAssemblyISD::CALL0 : WebAssemblyISD::CALL1,
446 if (Ins.empty()) {
500 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
511 for (const ISD::InputArg &In : Ins) {
|
| /external/llvm/lib/Transforms/Instrumentation/ |
| SanitizerCoverage.cpp | 478 Instruction *Ins = SplitBlockAndInsertIfThen(
480 IRB.SetInsertPoint(Ins);
|
| /external/llvm/lib/Transforms/Scalar/ |
| LoopInterchange.cpp | 91 Instruction *Ins = dyn_cast<Instruction>(I);
92 if (!Ins)
352 bool areAllUsesReductions(Instruction *Ins, Loop *L);
603 bool LoopInterchangeLegality::areAllUsesReductions(Instruction *Ins, Loop *L) {
604 return !std::any_of(Ins->user_begin(), Ins->user_end(), [=](User *U) -> bool {
727 Instruction *Ins = dyn_cast<Instruction>(PHI->getIncomingValue(0));
728 if (!Ins)
732 if (!isa<PHINode>(Ins) && isOuterLoopExitBlock)
836 const Instruction &Ins = *I
[all...] |
| StraightLineStrengthReduce.cpp | 93 Stride(nullptr), Ins(nullptr), Basis(nullptr) {}
96 : CandidateKind(CT), Base(B), Index(Idx), Stride(S), Ins(I),
119 Instruction *Ins;
226 return (Basis.Ins != C.Ins && // skip the same instruction
229 Basis.Ins->getType() == C.Ins->getType() &&
231 DT->dominates(Basis.Ins->getParent(), C.Ins->getParent()) &&
290 return isGEPFoldable(cast<GetElementPtrInst>(C.Ins), TTI, DL)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseRegisterInfo.cpp | 564 MachineBasicBlock::iterator Ins = MBB->begin();
566 if (Ins != MBB->end())
567 DL = Ins->getDebugLoc();
575 MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, MCID, BaseReg)
|
| /frameworks/compile/slang/ |
| slang_rs_reflection_cpp.cpp | 271 const RSExportForEach::InVec &Ins = ForEach->getIns();
272 for (RSExportForEach::InIter BI = Ins.begin(), EI = Ins.end();
[all...] |
| slang_rs_reflection.cpp | 861 const RSExportForEach::InVec &Ins = EF->getIns();
865 if (Ins.size() == 1) {
869 } else if (Ins.size() > 1) {
871 for (RSExportForEach::InIter BI = Ins.begin(), EI = Ins.end(); BI != EI;
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 270 const SmallVectorImpl<ISD::InputArg> &Ins) {
271 State.AnalyzeFormalArguments(Ins, CC_MSP430_AssignStack);
345 const SmallVectorImpl<ISD::InputArg> &Ins) {
346 State.AnalyzeCallResult(Ins, RetCC_MSP430);
370 &Ins,
381 return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
383 if (Ins.empty())
396 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
412 Outs, OutVals, Ins, dl, DAG, InVals)
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 81 /// same number of types as the Ins/Outs arrays in LowerFormalArguments,
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 789 static void VerifyVectorTypes(const SmallVectorImpl<ISD::InputArg> &Ins) {
790 for (unsigned i = 0; i < Ins.size(); ++i)
791 VerifyVectorType(Ins[i].VT, Ins[i].ArgVT);
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenRegisters.h | 93 std::pair<CompMap::iterator, bool> Ins =
104 return (Ins.second || Ins.first->second == B) ? nullptr
105 : Ins.first->second;
|
| CodeGenRegisters.cpp | 322 DenseMap<const CodeGenRegister*, CodeGenSubRegIndex*>::iterator Ins =
324 if (Ins->second == SI->first)
332 SI->first->getName() + " and " + Ins->second->getName());
[all...] |
| /external/llvm/include/llvm/TableGen/ |
| Record.h | [all...] |
| /external/llvm/lib/CodeGen/ |
| RegAllocGreedy.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonCommonGEP.cpp | 551 std::pair<NodeSymRel::iterator, bool> Ins = EqRel.insert(C);
552 (void)Ins;
553 assert(Ins.second && "Cannot add a class");
583 std::pair<ProjMap::iterator,bool> Ins = PM.insert(std::make_pair(&S, Min));
584 (void)Ins;
585 assert(Ins.second && "Cannot add minimal element");
[all...] |
| HexagonISelLowering.cpp | 615 SmallVectorImpl<ISD::InputArg> &Ins,
627 CCInfo.AnalyzeCallResult(Ins, RetCC_Hexagon);
650 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
695 Outs, OutVals, Ins, DAG);
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 370 const SmallVectorImpl<ISD::InputArg> &Ins,
375 return LowerFormalArguments_64(Chain, CallConv, IsVarArg, Ins,
377 return LowerFormalArguments_32(Chain, CallConv, IsVarArg, Ins,
388 const SmallVectorImpl<ISD::InputArg> &Ins,
400 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc32);
409 if (Ins[InIdx].Flags.isSRet()) {
596 const SmallVectorImpl<ISD::InputArg> &Ins,
606 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc64);
741 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
[all...] |
