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      1 //===-- Thumb2ITBlockPass.cpp - Insert Thumb-2 IT blocks ------------------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 
     10 #include "ARM.h"
     11 #include "ARMMachineFunctionInfo.h"
     12 #include "Thumb2InstrInfo.h"
     13 #include "llvm/ADT/SmallSet.h"
     14 #include "llvm/ADT/Statistic.h"
     15 #include "llvm/CodeGen/MachineFunctionPass.h"
     16 #include "llvm/CodeGen/MachineInstr.h"
     17 #include "llvm/CodeGen/MachineInstrBuilder.h"
     18 #include "llvm/CodeGen/MachineInstrBundle.h"
     19 using namespace llvm;
     20 
     21 #define DEBUG_TYPE "thumb2-it"
     22 
     23 STATISTIC(NumITs,        "Number of IT blocks inserted");
     24 STATISTIC(NumMovedInsts, "Number of predicated instructions moved");
     25 
     26 namespace {
     27   class Thumb2ITBlockPass : public MachineFunctionPass {
     28   public:
     29     static char ID;
     30     Thumb2ITBlockPass() : MachineFunctionPass(ID) {}
     31 
     32     bool restrictIT;
     33     const Thumb2InstrInfo *TII;
     34     const TargetRegisterInfo *TRI;
     35     ARMFunctionInfo *AFI;
     36 
     37     bool runOnMachineFunction(MachineFunction &Fn) override;
     38 
     39     const char *getPassName() const override {
     40       return "Thumb IT blocks insertion pass";
     41     }
     42 
     43   private:
     44     bool MoveCopyOutOfITBlock(MachineInstr *MI,
     45                               ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
     46                               SmallSet<unsigned, 4> &Defs,
     47                               SmallSet<unsigned, 4> &Uses);
     48     bool InsertITInstructions(MachineBasicBlock &MBB);
     49   };
     50   char Thumb2ITBlockPass::ID = 0;
     51 }
     52 
     53 /// TrackDefUses - Tracking what registers are being defined and used by
     54 /// instructions in the IT block. This also tracks "dependencies", i.e. uses
     55 /// in the IT block that are defined before the IT instruction.
     56 static void TrackDefUses(MachineInstr *MI,
     57                          SmallSet<unsigned, 4> &Defs,
     58                          SmallSet<unsigned, 4> &Uses,
     59                          const TargetRegisterInfo *TRI) {
     60   SmallVector<unsigned, 4> LocalDefs;
     61   SmallVector<unsigned, 4> LocalUses;
     62 
     63   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
     64     MachineOperand &MO = MI->getOperand(i);
     65     if (!MO.isReg())
     66       continue;
     67     unsigned Reg = MO.getReg();
     68     if (!Reg || Reg == ARM::ITSTATE || Reg == ARM::SP)
     69       continue;
     70     if (MO.isUse())
     71       LocalUses.push_back(Reg);
     72     else
     73       LocalDefs.push_back(Reg);
     74   }
     75 
     76   for (unsigned i = 0, e = LocalUses.size(); i != e; ++i) {
     77     unsigned Reg = LocalUses[i];
     78     for (MCSubRegIterator Subreg(Reg, TRI, /*IncludeSelf=*/true);
     79          Subreg.isValid(); ++Subreg)
     80       Uses.insert(*Subreg);
     81   }
     82 
     83   for (unsigned i = 0, e = LocalDefs.size(); i != e; ++i) {
     84     unsigned Reg = LocalDefs[i];
     85     for (MCSubRegIterator Subreg(Reg, TRI, /*IncludeSelf=*/true);
     86          Subreg.isValid(); ++Subreg)
     87       Defs.insert(*Subreg);
     88     if (Reg == ARM::CPSR)
     89       continue;
     90   }
     91 }
     92 
     93 /// Clear kill flags for any uses in the given set.  This will likely
     94 /// conservatively remove more kill flags than are necessary, but removing them
     95 /// is safer than incorrect kill flags remaining on instructions.
     96 static void ClearKillFlags(MachineInstr *MI, SmallSet<unsigned, 4> &Uses) {
     97   for (MachineOperand &MO : MI->operands()) {
     98     if (!MO.isReg() || MO.isDef() || !MO.isKill())
     99       continue;
    100     if (!Uses.count(MO.getReg()))
    101       continue;
    102     MO.setIsKill(false);
    103   }
    104 }
    105 
    106 static bool isCopy(MachineInstr *MI) {
    107   switch (MI->getOpcode()) {
    108   default:
    109     return false;
    110   case ARM::MOVr:
    111   case ARM::MOVr_TC:
    112   case ARM::tMOVr:
    113   case ARM::t2MOVr:
    114     return true;
    115   }
    116 }
    117 
    118 bool
    119 Thumb2ITBlockPass::MoveCopyOutOfITBlock(MachineInstr *MI,
    120                                       ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
    121                                         SmallSet<unsigned, 4> &Defs,
    122                                         SmallSet<unsigned, 4> &Uses) {
    123   if (!isCopy(MI))
    124     return false;
    125   // llvm models select's as two-address instructions. That means a copy
    126   // is inserted before a t2MOVccr, etc. If the copy is scheduled in
    127   // between selects we would end up creating multiple IT blocks.
    128   assert(MI->getOperand(0).getSubReg() == 0 &&
    129          MI->getOperand(1).getSubReg() == 0 &&
    130          "Sub-register indices still around?");
    131 
    132   unsigned DstReg = MI->getOperand(0).getReg();
    133   unsigned SrcReg = MI->getOperand(1).getReg();
    134 
    135   // First check if it's safe to move it.
    136   if (Uses.count(DstReg) || Defs.count(SrcReg))
    137     return false;
    138 
    139   // If the CPSR is defined by this copy, then we don't want to move it. E.g.,
    140   // if we have:
    141   //
    142   //   movs  r1, r1
    143   //   rsb   r1, 0
    144   //   movs  r2, r2
    145   //   rsb   r2, 0
    146   //
    147   // we don't want this to be converted to:
    148   //
    149   //   movs  r1, r1
    150   //   movs  r2, r2
    151   //   itt   mi
    152   //   rsb   r1, 0
    153   //   rsb   r2, 0
    154   //
    155   const MCInstrDesc &MCID = MI->getDesc();
    156   if (MI->hasOptionalDef() &&
    157       MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR)
    158     return false;
    159 
    160   // Then peek at the next instruction to see if it's predicated on CC or OCC.
    161   // If not, then there is nothing to be gained by moving the copy.
    162   MachineBasicBlock::iterator I = MI; ++I;
    163   MachineBasicBlock::iterator E = MI->getParent()->end();
    164   while (I != E && I->isDebugValue())
    165     ++I;
    166   if (I != E) {
    167     unsigned NPredReg = 0;
    168     ARMCC::CondCodes NCC = getITInstrPredicate(I, NPredReg);
    169     if (NCC == CC || NCC == OCC)
    170       return true;
    171   }
    172   return false;
    173 }
    174 
    175 bool Thumb2ITBlockPass::InsertITInstructions(MachineBasicBlock &MBB) {
    176   bool Modified = false;
    177 
    178   SmallSet<unsigned, 4> Defs;
    179   SmallSet<unsigned, 4> Uses;
    180   MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
    181   while (MBBI != E) {
    182     MachineInstr *MI = &*MBBI;
    183     DebugLoc dl = MI->getDebugLoc();
    184     unsigned PredReg = 0;
    185     ARMCC::CondCodes CC = getITInstrPredicate(MI, PredReg);
    186     if (CC == ARMCC::AL) {
    187       ++MBBI;
    188       continue;
    189     }
    190 
    191     Defs.clear();
    192     Uses.clear();
    193     TrackDefUses(MI, Defs, Uses, TRI);
    194 
    195     // Insert an IT instruction.
    196     MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(ARM::t2IT))
    197       .addImm(CC);
    198 
    199     // Add implicit use of ITSTATE to IT block instructions.
    200     MI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/,
    201                                              true/*isImp*/, false/*isKill*/));
    202 
    203     MachineInstr *LastITMI = MI;
    204     MachineBasicBlock::iterator InsertPos = MIB.getInstr();
    205     ++MBBI;
    206 
    207     // Form IT block.
    208     ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC);
    209     unsigned Mask = 0, Pos = 3;
    210 
    211     // v8 IT blocks are limited to one conditional op unless -arm-no-restrict-it
    212     // is set: skip the loop
    213     if (!restrictIT) {
    214       // Branches, including tricky ones like LDM_RET, need to end an IT
    215       // block so check the instruction we just put in the block.
    216       for (; MBBI != E && Pos &&
    217              (!MI->isBranch() && !MI->isReturn()) ; ++MBBI) {
    218         if (MBBI->isDebugValue())
    219           continue;
    220 
    221         MachineInstr *NMI = &*MBBI;
    222         MI = NMI;
    223 
    224         unsigned NPredReg = 0;
    225         ARMCC::CondCodes NCC = getITInstrPredicate(NMI, NPredReg);
    226         if (NCC == CC || NCC == OCC) {
    227           Mask |= (NCC & 1) << Pos;
    228           // Add implicit use of ITSTATE.
    229           NMI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/,
    230                                                  true/*isImp*/, false/*isKill*/));
    231           LastITMI = NMI;
    232         } else {
    233           if (NCC == ARMCC::AL &&
    234               MoveCopyOutOfITBlock(NMI, CC, OCC, Defs, Uses)) {
    235             --MBBI;
    236             MBB.remove(NMI);
    237             MBB.insert(InsertPos, NMI);
    238             ClearKillFlags(MI, Uses);
    239             ++NumMovedInsts;
    240             continue;
    241           }
    242           break;
    243         }
    244         TrackDefUses(NMI, Defs, Uses, TRI);
    245         --Pos;
    246       }
    247     }
    248 
    249     // Finalize IT mask.
    250     Mask |= (1 << Pos);
    251     // Tag along (firstcond[0] << 4) with the mask.
    252     Mask |= (CC & 1) << 4;
    253     MIB.addImm(Mask);
    254 
    255     // Last instruction in IT block kills ITSTATE.
    256     LastITMI->findRegisterUseOperand(ARM::ITSTATE)->setIsKill();
    257 
    258     // Finalize the bundle.
    259     finalizeBundle(MBB, InsertPos.getInstrIterator(),
    260                    ++LastITMI->getIterator());
    261 
    262     Modified = true;
    263     ++NumITs;
    264   }
    265 
    266   return Modified;
    267 }
    268 
    269 bool Thumb2ITBlockPass::runOnMachineFunction(MachineFunction &Fn) {
    270   const ARMSubtarget &STI =
    271       static_cast<const ARMSubtarget &>(Fn.getSubtarget());
    272   if (!STI.isThumb2())
    273     return false;
    274   AFI = Fn.getInfo<ARMFunctionInfo>();
    275   TII = static_cast<const Thumb2InstrInfo *>(STI.getInstrInfo());
    276   TRI = STI.getRegisterInfo();
    277   restrictIT = STI.restrictIT();
    278 
    279   if (!AFI->isThumbFunction())
    280     return false;
    281 
    282   bool Modified = false;
    283   for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E; ) {
    284     MachineBasicBlock &MBB = *MFI;
    285     ++MFI;
    286     Modified |= InsertITInstructions(MBB);
    287   }
    288 
    289   if (Modified)
    290     AFI->setHasITBlocks(true);
    291 
    292   return Modified;
    293 }
    294 
    295 /// createThumb2ITBlockPass - Returns an instance of the Thumb2 IT blocks
    296 /// insertion pass.
    297 FunctionPass *llvm::createThumb2ITBlockPass() {
    298   return new Thumb2ITBlockPass();
    299 }
    300